Proper way to make LUT ROMs

[hackguy25]

I want to make a LUT ROM to drive an LED matrix. So far I've written something like this:

wire [0:63] b2_inner;
always @* begin
    casex (line)
        5'b00000: b2_inner = 64'h00000001f8000730;
        5'b00001: b2_inner = 64'h00000000fe001fc0;
        5'b00010: b2_inner = 64'h000000007fc0ff80;
        5'b00011: b2_inner = 64'h000000001ffffe00;
        5'b00100: b2_inner = 64'h0000000007fff800;
        5'b00101: b2_inner = 64'h0000000001ffe000;
        5'b0011x: b2_inner = 64'h0000000000000000;
        5'b01xxx: b2_inner = 64'h0000000000000000;
        5'b1xxxx: b2_inner = 64'h0000000000000000;
    endcase
    b2 = b2_inner[column];
end

where b2 is the final output for a given line and column. Yosys gives me these warnings:

Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:191.19-191.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:192.19-192.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:193.19-193.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:194.19-194.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:195.19-195.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:196.19-196.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:197.19-197.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:198.19-198.50.
Warning: wire '\b2_inner' is assigned in a block at includes/three_rings.v:199.19-199.50.
Warning: wire '\b2' is assigned in a block at includes/three_rings.v:201.5-201.26.

Basically, I want to have a combinatorial circuit (without latches) that gives me an output signal depending on the input coordinates. Is there a proper way to do this?

[nakengelhardt]

The warning is just complaining that it's a syntax error to declare a signal as wire and then assign it in an always block. You have to use the reg keyword in that case. Other than that the code does get interpreted as a combinatorial circuit and doesn't infer any latches, e.g. if I just put it in its own module and run synth_ice40 on that, the final stat shows it's converted into only LUTs:

   Number of cells:                 40
     SB_LUT4                        40

And it even explicitly notes that your code does not model any latch:

2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\top.\b2' from process `\top.$proc$top.v:8$1'.
No latch inferred for signal `\top.\b2_inner' from process `\top.$proc$top.v:8$1'.

So at least in that regard everything seems to be working as intended.

There is the proc_rom pass (part of proc which is part of all synth_* commands) which will convert case statements into memories rather than muxes. proc_rom doesn't do the transformation if any of the cases has X bits (the optimization of combining many cases together is assumed to be more useful than the gains from inferring a block ram).

In general if you are targeting a specific memory style the supported patterns for how to write them are here in the documentation.

[hackguy25]

Great! Thank you for the answer!