Discussions

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  Ensuring module output ports are always a single net, not a concatenation of nets

  gussmith23 asked Aug 21, 2024 in Q&A · Unanswered

  

  

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  Correct cleanup of debug code

  pat-pgt started Aug 12, 2024 in General

  

  

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  Example of write_aiger working with assert

  gjasper asked Aug 12, 2024 in Q&A · Unanswered

  

  

  

  

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  Issue with Generating bad Statements in BTOR2 Files Using Yosys

  EPTansuo asked Aug 4, 2024 in Q&A · Answered

  

  

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  cannot synthesize latch?

  lacary started May 16, 2024 in General

  

  

  

  

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  Hard Macros, etc.

  stacksmith asked Aug 8, 2024 in Q&A · Unanswered

  

  

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  Verilog package manager

  sathvikr started Aug 6, 2024 in Show and tell

  

  

  

  

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  How to debug in vscode of my handwrite pass

  hanm2019 asked Jul 10, 2024 in Q&A · Closed · Unanswered

  

  

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  Polarfire

  liamdiprose asked Jan 6, 2024 in Q&A · Answered

  

  

  

  

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  CDC detection with yosys

  ldoolitt started Sep 25, 2023 in Show and tell

  

  

  

  

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  Using splitnets only on selection

  A-Kibats asked Jul 16, 2024 in Q&A · Unanswered

  

  

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  Writing Match for EQY.

  Ajaymalolan asked Jun 26, 2024 in Q&A · Unanswered

  

  

  

  

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  Correct yosys usage

  janetatomas1 asked Jul 12, 2024 in Q&A · Unanswered

  

  

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  How to configure yosys to code fsm in binary (and no one-hot)

  titan73 asked Jun 19, 2024 in Q&A · Closed · Answered

  

  

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  Is there a way to pull out from a module a vector which represents all the DFFs in the module and it's submodules

  Topi-ab started Jul 10, 2024 in General

  

  

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  DFF naming of multi-dimensional array

  titan73 asked Jun 18, 2024 in Q&A · Unanswered

  

  

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  naming rule for the synthesised verilog

  nlwmode asked Jun 14, 2024 in Q&A · Answered

  

  

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  Force inference of BRAMs

  nachiket started Jun 11, 2024 in General

  

  

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  Proper way to make LUT ROMs

  hackguy25 asked Jun 6, 2024 in Q&A · Answered

  

  

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  How to synthesize logic gates with 3 or more inputs?

  mivuzz asked May 27, 2024 in Q&A · Unanswered

  

  

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  How to map the circuit into LUT and DFF in yosys？

  thn-pudding asked May 5, 2023 in Q&A · Closed · Answered

  

  

  

  

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  How to add SystemVerilog package to yosys synthesis?

  TarikHamedovic asked May 22, 2024 in Q&A · Closed · Unanswered

  

  

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  How to extract an AST tree？

  lijiale6224 started Oct 29, 2023 in General

  

  

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  Outputs differ before and after synthesis, but Yosys seems correct.

  pending-verification This issue is pending verification and/or reproduction

  WeneneW asked May 15, 2024 in Q&A · Unanswered

  

  

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  how does yosys synthesize initial blocks

  pm100 started May 11, 2024 in General

  

  

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