pseudo_random_sequence_generator(5-bit)

LFSR behavioural model in Verilog.

for longest 5-bits repeating sequence, tapping done at 2nd and 5th flip-flop.

Coded in EDAplayground.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
README.md		README.md
a.out		a.out
design.sv		design.sv
random.vcd		random.vcd
testbench.sv		testbench.sv

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