32-Bit-RISC-V-based-CPU

Designed a 32-Bit RISC-V ISA based 5-Stage pipelined CPU in 5 days!! The design involved TL-Verilog coding for a simple pipelined calculator and addressed all the hazards.

Below are the tasks performed in 5-Day worksop -

DAY-1 - Introduction to RISC-V ISA and GNU compiler toolchain

1. Introduction to RISC-V basic keywords
2. Labwork for RISC-V software toolchain
3. Integer number representation
4. Signed and unsigned arithmetic operations

DAY-2 - Introduction to ABI and basic verification flow

1. Application Binary interface (ABI)
2. Lab work using ABI function calls
3. Basic verification flow using iverilog

DAY-3 - Digital Logic with TL-Verilog and Makerchip (http://makerchip.com/)

1. Combinational logic in TL-Verilog using Makerchip
2. Sequential and pipelined logic
3. Validity
4. Hierarchy

DAY-4 - Basic RISC-V CPU micro-architecture

1. Microarchitecture and testbench for a simple RISC-V CPU
2. Fetch, decode, and execute logic
3. RISC-V control logic

DAY-5 - Complete Pipelined RISC-V CPU micro-architecture/store

1. Pipelining the CPU
2. Load and store instructions and memory
3. Completing the RISC-V CPU

CPU Block

Pipeline Architecture

Instructions and Register values

Makerchip