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  1. 512-Bit-SRAM 512-Bit-SRAM Public

    Design of 512-Bit SRAM using four 128bits banks using Cadence Virtuoso

    5

  2. 16-Bit_CPU_Design 16-Bit_CPU_Design Public

    Designed, Simulated and Synthesized a 16-Bit CPU in Verilog HDL. The design involved RTL coding for counter, ALU, CPU controller, Instruction register and data memory.

    Verilog 1

  3. 32-Bit-RISC-V-based-CPU 32-Bit-RISC-V-based-CPU Public

    Designed a 32-Bit RISC-V ISA based 5-Stage pipelined CPU in 5 days!! The design involved TL-Verilog coding for a simple pipelined calculator and addressed all the hazards.

    C 1

  4. 8-Bit-Microprocessor 8-Bit-Microprocessor Public

    Design of 8-bit microprocessor for 600nm technology using Cadence Virtuoso

  5. highlight-text highlight-text Public

    Forked from brianmcallister/highlight-text

    Highlight `words` in some `text`

    TypeScript