Standard Cell Library based Memory Compiler using FF/Latch cells
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Updated
Jun 15, 2024 - Verilog
Standard Cell Library based Memory Compiler using FF/Latch cells
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys
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