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Issues: AUCOHL/DFFRAM
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Document the difference between "DFFRAM Compiler" and "DFFRAM/OpenLane"
#171
opened Nov 26, 2022 by
xobs
Row decoder logic messing up the placement of arrays where row size is a multiple of word size.
#144
opened Mar 21, 2022 by
donnie-j
Use Sphinx to create awesome documentation for the project
documentation
Improvements or additions to documentation
enhancement
New feature or request
#131
opened Feb 3, 2022 by
mithro
Support generation of FIFO / ring buffer style memories for queues
enhancement
New feature or request
#129
opened Feb 3, 2022 by
mithro
Add support for ASAP7 open source PDK
blocked
enhancement
New feature or request
#128
opened Feb 3, 2022 by
mithro
Small RAMs might not intersect all met5 power rails
enhancement
New feature or request
#122
opened Dec 21, 2021 by
antonblanchard
dffram should be exposed a regular python module
enhancement
New feature or request
#120
opened Dec 13, 2021 by
proppy
dffram should allow pointing to a local openlane install
enhancement
New feature or request
#119
opened Dec 13, 2021 by
proppy
128x64 3R1W Register File for Microwatt
enhancement
New feature or request
#108
opened Sep 29, 2021 by
antonblanchard
Technology Porting Instructions
documentation
Improvements or additions to documentation
#103
opened Aug 1, 2021 by
leochand101
Generate and Characterize Lib Files
enhancement
New feature or request
#55
opened Jun 1, 2021 by
donn
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