Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
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Updated
Aug 23, 2024 - C
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
Interfacing VHDL and foreign languages with VUnit
GTKWave Decoders for RISCV
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
Cosimulator for the Violet core: https://github.com/losfair/Violet
Set of utilities to export/import FMUs out of existing C++ code
Enables the co-simulation between PSS/E and Matlab/Simulink
CoSys MAP 2020: Integrating Physical and Virtual Objects in a Simulation Environment
CoSimo dreams of becoming a co-simulation compositor for generic simulations.
Integration test between Verilog and C++ using VPI
coherence integrates evolutionary computation and co-simulation for the systematic design of protocols for cell culture and biofabrication.
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