VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
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Updated
Dec 17, 2019 - VHDL
VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
FPGA implementation of the popular logic game using VHDL and Altera DE1
An 8-bit processor in VHDL based on a simple instruction set
Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.
Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.
Hardware Praktikum at Uni Freiburg
A simple sram controller and test for the altera DE1 FPGA board
Digital clock in VHDL, on Altera Cyclone IV FPGA Board A-C4E6. This work was presented on PLP discipline during electrical engineer course at Mackenzie Presbyterian University.
Pong VGA for a DE0 Altera model FPGA programmed in VHDL.
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
FPGA and CPLD programming, tutorials and information I figure out.
Lab exercises on digital circuit design using Altera Quartus 9.1sp2
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
A scalable and freely configurable function generator in VHDL
Team 21 - Mini-Project
The work presented is designed to simulate the operation of an automatic coffee machine. It will manage the machine operation by exploiting the processing capabilities of the FPGA.
A firmware was written in VHDL to display all the characters from the ASCII table to the display.
a state-machine based implementation of a multiplayer battle simulator on an Altera FPGA using VGA video output
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