Add Verilog support #3
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ModelSim ( On the other hand, pure syntax checking via Icarus Verilog should be reasonable. |
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For VHDL/Verilog exclusive pairs, maybe it's feasible to translate at least the VHDL entity or Verilog module definition to the other language to allow basic port map checks. |
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* Issue #3 - add Verilog support is work in progress * Added file_types attribute to fallback builder * Fixing import paths * Added option to run tests without deleting its venv * Fixing bugs/tests inserted after Verilog support. This is still work in progress... * Handling .svh file extension as systemverilog * Fixed some issues on build flags for different languages * Builder test now use specific sources * Replacing external test files for local ones * Adding builder test for Verilog and SystemVerilog * Adjusts for VUnit and SystemVerilog * Possible fix for source parser pool hanging * Fixes for SystemVerilog and VUnit * Testing fix for hanging tests * Adding copyright to files * Test skips are now done via unittest.skip decorator * Fixes to VUnit and Verilog/SystemVerilog * Adding copyright * Minor style fixes * Cleaning up unused code * Builders don't need to declare empty default options * Updating ghdl from 0.31 to 0.33 * Improved diag handler * Adding verilog source parser tests * Including hdlcc.tests.test_misc in standalone execution * Removing VUnit from tests it is not required * Removed external CI dependencies * Fixing some hangs when using multiprocessing.Pool
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Fixed as per PR #29. |
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Minimal steps to add Verilog support:
vcomvsvlogfor instance)The text was updated successfully, but these errors were encountered: