v1.5.9

This list shows the main core changes since the last release. See the project's changelog for more information.

🐛 Bug Fixes

• ⚠️ fixed major bug in CPU interrupt system: interrupts during memory accesses broke those memory accesses leading to undefined behavior
• fixed bug in E ISA extension that prevented the extension to be actually enabled
• fixed bug in linker script (#134): missing constant data section
• fixed bug in AXI4-Lite wrapper (#133) that caused failure of Vivado packaging
• fixed bug in execution of xRET instructions (trapping of MRET and DRET when not in according mode was missing)

💡 Updates and New Features

• ⚠️ top entity machine-level interrupts now trigger on rising edges (mext_irq_i, msw_irq_i, mtime_irq_i, nm_irq_i)
• exposed advanced external bus interface configuration options as new top entity generics (moved from package constants): MEM_EXT_PIPE_MODE, MEM_EXT_BIG_ENDIAN, MEM_EXT_ASYNC_RX
• added mstatus.TW CSR flag (to allow execution of wfi in user machine mode)
• added mstatus.FS and mstatus.SD CSR bits to control the state of the FPU (Zfinx extension)
• added mconfigptr CSR (not actually used yet, read-only, always zero)
• reworked CPU register file ("implementation" of zero register)
• clean-up of processor top's generic and signals default values

✔️ Pull Requests and Issues

Merged pull requests:

• none

Closed issues:

• #133 Problems generating a Vivado-Block Design
• #134 Missing memory section for .rodata in neorv32.ld