[rtl] Try to fix Quartus latch warnings

[stnolting]

Quartus 21.1 shows the following message:

Warning (10631): VHDL Process Statement warning at neorv32_cpu_control.vhd(1635): inferring latch(es) for signal or variable "csr", which holds its previous value in one or more paths through the process

But there are no latches in the code! The CSR read and write processes are entirely synchronous. Furthermore, the synthesis report does not show any latches (Compilation Report -> Analysis & Synthesis -> Optimization Results -> Register Statistics).

This PR tries to fix this issue by reformatting certain parts of the VHDL code.

See discussion #421 for more information.