[rtl] Try to fix Quartus latch warnings (#434)

stnolting · Oct 25, 2022 · b3ba2a6 · b3ba2a6
2 parents 24e884e + 5cbf4b7
commit b3ba2a6
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Showing 3 changed files with 68 additions and 10 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -32,6 +32,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 24.10.2022 | 1.7.7.5 | :test_tube: remove weird Quartus latch warnings by modifying VHDL coding style; [#434](https://github.com/stnolting/neorv32/pull/434) |
 | 19.10.2022 | 1.7.7.4 | optimize UART's `RTS` (hardware flow control) behavior; [#433](https://github.com/stnolting/neorv32/pull/433) |
 | 15.10.2022 | 1.7.7.3 | :bug: fix bug in `is_power_of_two_f` VHDL function (thanks Alan!); [#482](https://github.com/stnolting/neorv32/pull/428) |
 | 12.10.2022 | 1.7.7.2 | add dedicated hardware reset to _all_ CPU counters (`[m]cycle[h]`, `[m]instret[h]`, `[m]hpmcounter[h]`); :sparkles: **all CSRs now provide a dedicated hardware reset**; [#426](https://github.com/stnolting/neorv32/pull/426) |

diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
@@ -1501,6 +1501,11 @@ begin
           trap_ctrl.exc_buf(exc_db_hw_c)    <= (trap_ctrl.exc_buf(exc_db_hw_c)    or debug_ctrl.trig_hw)    and (not trap_ctrl.env_start_ack);
           trap_ctrl.irq_buf(irq_db_halt_c)  <= debug_ctrl.trig_halt;
           trap_ctrl.irq_buf(irq_db_step_c)  <= debug_ctrl.trig_step;
+        else
+          trap_ctrl.exc_buf(exc_db_break_c) <= '0';
+          trap_ctrl.exc_buf(exc_db_hw_c)    <= '0';
+          trap_ctrl.irq_buf(irq_db_halt_c)  <= '0';
+          trap_ctrl.irq_buf(irq_db_step_c)  <= '0';
         end if;
 
         -- interrupt buffer: machine software/external/timer interrupt --
@@ -1647,6 +1652,7 @@ begin
       csr.mepc              <= (others => '0');
       csr.mcause            <= (others => '0');
       csr.mtval             <= (others => '0');
+      --
       csr.mip_firq_nclr     <= (others => '-'); -- no reset required
       --
       csr.pmpcfg            <= (others => (others => '0'));
@@ -1684,9 +1690,10 @@ begin
       csr.mip_firq_nclr <= (others => '1'); -- active low
 
       if (CPU_EXTENSION_RISCV_Zicsr = true) then
-        -- --------------------------------------------------------------------------------
-        -- CSR access by application software
-        -- --------------------------------------------------------------------------------
+
+        -- ********************************************************************************
+        -- Manual CSR access by application software
+        -- ********************************************************************************
         if (csr.we = '1') then -- manual write access and not illegal instruction
 
           -- user floating-point CSRs --
@@ -1759,7 +1766,7 @@ begin
             end if;
           end if;
 
-          -- physical memory protection --
+          -- machine physical memory protection --
           -- --------------------------------------------------------------------
           if (PMP_NUM_REGIONS > 0) then
             -- R/W: pmpcfg* - PMP configuration registers --
@@ -1842,7 +1849,7 @@ begin
             end if;
           end if;
 
-          -- trigger module CSRs - only writable in DEBUG MODE (dmode == 1) --
+          -- trigger module CSRs - writable only in DEBUG MODE (dmode == 1) --
           -- --------------------------------------------------------------------
           if (CPU_EXTENSION_RISCV_DEBUG = true) then
             if (csr.addr(11 downto 4) = csr_class_trigger_c) then -- trigger CSR class
@@ -1860,9 +1867,9 @@ begin
           end if;
 
 
-        -- --------------------------------------------------------------------------------
-        -- CSR access by hardware
-        -- --------------------------------------------------------------------------------
+        -- ********************************************************************************
+        -- Automatic CSR access by hardware
+        -- ********************************************************************************
         else
 
           -- --------------------------------------------------------------------
@@ -1960,7 +1967,57 @@ begin
           end if;
 
         end if; -- /hardware csr access
-      end if;
+
+
+        -- ********************************************************************************
+        -- Override - tie unimplemented registers to all-zero
+        -- ********************************************************************************
+
+        -- no FPU --
+        if (CPU_EXTENSION_RISCV_Zfinx = false) then
+          csr.frm    <= (others => '0');
+          csr.fflags <= (others => '0');
+        end if;
+
+        -- no user mode --
+        if (CPU_EXTENSION_RISCV_U = false) then
+          csr.mstatus_mpp  <= '0';
+          csr.mstatus_mprv <= '0';
+          csr.mstatus_tw   <= '0';
+          --
+          csr.mcounteren_cy <= '0';
+          csr.mcounteren_tm <= '0';
+          csr.mcounteren_ir <= '0';
+          --
+          csr.dcsr_ebreaku <= '0';
+          csr.dcsr_prv     <= '0';
+        end if;
+
+        -- no PMP --
+        if (PMP_NUM_REGIONS = 0) then
+          csr.pmpcfg  <= (others => (others => '0'));
+          csr.pmpaddr <= (others => (others => '0'));
+        end if;
+
+        -- no HPMs --
+        if (HPM_NUM_CNTS = 0) or (CPU_EXTENSION_RISCV_Zihpm = false) then
+          csr.mcountinhibit_hpm <= (others => '0');
+          csr.mhpmevent         <= (others => (others => '0'));
+        end if;
+
+        -- no debug mode --
+        if (CPU_EXTENSION_RISCV_DEBUG = false) then
+          csr.dcsr_ebreakm <= '0';
+          csr.dcsr_step    <= '0';
+          csr.dcsr_ebreaku <= '0';
+          csr.dcsr_prv     <= priv_mode_m_c;
+          csr.dpc          <= (others => '0');
+          csr.dscratch0    <= (others => '0');
+          csr.tdata1_exe   <= '0';
+          csr.tdata2       <= (others => '0');
+        end if;
+
+      end if; -- /Zicsr implemented
     end if;
   end process csr_write_access;
 

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -58,7 +58,7 @@ package neorv32_package is
 
   -- Architecture Constants (do not modify!) ------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070704"; -- NEORV32 version - no touchy!
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070705"; -- NEORV32 version - no touchy!
   constant archid_c     : natural := 19; -- official RISC-V architecture ID - hands off!
 
   -- Check if we're inside the Matrix -------------------------------------------------------