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[rtl] add "async TX" Wishbone option #352

Merged
merged 5 commits into from
Jun 22, 2022
Merged

[rtl] add "async TX" Wishbone option #352

merged 5 commits into from
Jun 22, 2022

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stnolting
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@stnolting stnolting commented Jun 21, 2022

This PR adds another configuration option for the external memory interface (Wishbone). By default, all incoming and outgoing Wishbone signals are registered to allow easy timing closure even when using complex (combinatorial) Wishbone interconnection networks.

The processor already provides the MEM_EXT_ASYNC_RX option to omit the register stage for incoming signals (seen from the processor). The new MEM_EXT_ASYNC_TX option now allows to also omit the register stage for outgoing signals.

Each enabled option will reduce the external memory interface latency by 1 cycle. If both options are enabled an external memory can be accessed with the same latency as any processor-internal memory.

@stnolting stnolting added enhancement New feature or request HW hardware-related labels Jun 21, 2022
@stnolting stnolting self-assigned this Jun 21, 2022
@stnolting stnolting marked this pull request as ready for review June 21, 2022 19:24
@stnolting stnolting merged commit 28d1e81 into main Jun 22, 2022
@stnolting stnolting deleted the wishbone_async_tx branch June 22, 2022 09:03
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