[B ISA extension] add carry-less multiply instructions (Zbc) support #260
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stnolting
added
enhancement
added Zbc ISA extension to CPU
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This PR is a follow-up of #259 and adds the last missing sub-extension to the CPU's RISC-V bit-manipulation ISA extension "
B":Zbc- carry-less multiplication instructionsThe NEORV32 CPU now supports all four
Bsubsets (according to the recently frozen and ratified RISC-V bit-manipulation spec. v0.93/v1.00):Zbb- basic bit-manipulation instructionsZba- address-generation instructionsZbs- single-bit instructionsZbc- carry-less multiplication instructions📚 A copy of the RISC-V
Bspec (v0.93) can be found in docs/references.Since there is no upstream gcc support yet,
Zbcintrinsics and emulation functions have been added tosw/example/bitmanip_test/neorv32_b_extension_intrinsics.h. Furthermore, according test cases have been added tosw/example/bitmanip_test/main.cto verify correct operations.