[B ISA extension] add single-bit instructions (Zbs) support #259
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stnolting
added
enhancement
Added RISC-V Zbs (bit-manipulation's single-bit instructions) support
added basic infrastructure for upcoming (?) Zbc sub-extension
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This PR adds another sub-extension to the recently ratified RISC-V bit-manipulation ISA extension "
B":Zbs- single-bit instructionsThe NEORV32 CPU now supports three of the four
Bsubsets (if the bit-manipulation is enabled by setting theCPU_EXTENSION_RISCV_Btop generic true):Zbb- basic bit-manipulation instructionsZba- address-computation instructionsZbs- single-bit instructionsZbc- carry-less multiplication instructions - not supported yet (but coming soon)Since there is no upstream gcc support yet,
Zbsintrinsics and emulation functions have been added tosw/example/bitmanip_test/neorv32_b_extension_intrinsics.hto verify correct operations. Furthermore, according test cases have been added tosw/example/bitmanip_test/main.c. The new testcases also check that instructions from theZbcsubset do raise an illegal instruction exception (as they are not supported yet).🐛 This PR also fixes a minor bug in the CPU's co-processor arbitration logic: multi-cycle ALU operations (= CPU co-processor operations) that are triggered by an illegal instruction are allowed to complete execution even though there will be no data committed (for example no register file write-back). This is required to ensure that no co-processor operation is still in progress when the CPU enters trap state.