⚠️ [makefile] modify handling of MARCH and MABI variables

.github/workflows/Processor.yml

@@ -60,7 +60,7 @@ jobs:
           USER_FLAGS+=-DRUN_CHECK
           USER_FLAGS+=-DUART0_SIM_MODE
           USER_FLAGS+=-DSUPPRESS_OPTIONAL_UART_PRINT
-          MARCH=-march=rv32imac
+          MARCH=rv32imac
           info
           all
 

.github/workflows/Windows.yml

@@ -106,7 +106,7 @@ jobs:
           USER_FLAGS+=-DRUN_CHECK \
           USER_FLAGS+=-DUART0_SIM_MODE \
           USER_FLAGS+=-DSUPPRESS_OPTIONAL_UART_PRINT \
-          MARCH=-march=rv32imac \
+          MARCH=rv32imac \
           info \
           all
 

CHANGELOG.md

@@ -26,6 +26,7 @@ defined by the `hw_version_c` constant in the main VHDL package file [`rtl/core/
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:----------:|:-------:|:--------|
+| 15.10.2021 | 1.6.1.12 | :warning: :warning: main software makefile: modified behavior of `MARCH` and `MABI` variables - the `-march` and `-mabi` flags are no longer required/allowed (example: overriding makefile's default `MARCH` is now done using `make MARCH=rv32imac ...`) ([see PR #184](https://github.com/stnolting/neorv32/pull/184)) |
 | 15.10.2021 | 1.6.1.12 | :warning: Custom Functions Subsystem (CFS): removed `sleep` input (indicating CPU is in sleep mode); minor CPU control logic optimization |
 | 15.10.2021 | 1.6.1.11 | :sparkles: UARTs: added optional configurable RX and TX FIFOs, added fine-grained RX/TX IRQ configuration options (see [PR #183](https://github.com/stnolting/neorv32/pull/183)) |
 | 14.10.2021 | 1.6.1.10 | :sparkles: SLINK: added fine-grained, per-link interrupt configuration (see [PR #182](https://github.com/stnolting/neorv32/pull/182)) |

do.py

@@ -27,7 +27,7 @@ def task_BuildAndInstallSoftwareFrameworkTests():
             # Compile and install test application
             # Redirect UART0 TX to text.io simulation output via <UART0_SIM_MODE> user flag
             "echo 'Compiling and installing CPU (/Processor) test application'",
-            "make -C sw/example/processor_check clean_all USER_FLAGS+=-DRUN_CHECK USER_FLAGS+=-DUART0_SIM_MODE USER_FLAGS+=-DUART1_SIM_MODE MARCH=-march=rv32imac info all",
+            "make -C sw/example/processor_check clean_all USER_FLAGS+=-DRUN_CHECK USER_FLAGS+=-DUART0_SIM_MODE USER_FLAGS+=-DUART1_SIM_MODE MARCH=rv32imac info all",
         ],
         "doc": "Build all sw/example/*; install bootloader and processor check",
     }

docs/datasheet/cpu.adoc

@@ -470,7 +470,7 @@ Note that `M` and `Zmmul` extensions _cannot_ be enabled at the same time.
 [TIP]
 If your RISC-V GCC toolchain does not (yet) support the `_Zmmul` ISA extensions, it can be "emulated"
 using a `rv32im` machine architecture and setting the `-mno-div` compiler flag
-(example `$ make MARCH=-march=rv32im USER_FLAGS+=-mno-div clean_all exe`).
+(example `$ make MARCH=rv32im USER_FLAGS+=-mno-div clean_all exe`).
 
 
 ==== **`U`** - Less-Privileged User Mode

docs/datasheet/software.adoc

@@ -144,7 +144,7 @@ makefile (`sw/common/common.mk`):
 
 [TIP]
 The makefile configuration variables can be (re-)defined directly when invoking the makefile. For
-example via `$ make MARCH=-march=rv32ic clean_all exe`. You can also make project-specific definitions
+example via `$ make MARCH=rv32ic clean_all exe`. You can also make project-specific definitions
 of all variables inside the project's actual makefile (e.g., `sw/example/blink_led/makefile`).
 
 [source,makefile]
@@ -164,8 +164,8 @@ EFFORT ?= -Os
 # Compiler toolchain
 RISCV_PREFIX ?= riscv32-unknown-elf-
 # CPU architecture and ABI
-MARCH ?= -march=rv32i
-MABI  ?= -mabi=ilp32
+MARCH ?= rv32i
+MABI  ?= ilp32
 # User flags for additional configuration (will be added to compiler flags)
 USER_FLAGS ?=
 # Relative or absolute path to the NEORV32 home folder
@@ -181,7 +181,7 @@ NEORV32_HOME ?= ../../..
 | _ASM_INC_         | Include file folders that are used only for the assembly source files (`*.S`/`*.s`).
 | _EFFORT_          | Optimization level, optimize for size (`-Os`) is default; legal values: `-O0`, `-O1`, `-O2`, `-O3`, `-Os`
 | _RISCV_PREFIX_    | The toolchain prefix to be used; follows the naming convention "architecture-vendor-output-"
-| _MARCH_           | The targetd RISC-V architecture/ISA. Only `rv32` is supported by the NEORV32. Enable compiler support of optional CPU extension by adding the according extension letter (e.g. `rv32im` for _M_ CPU extension). See https://stnolting.github.io/neorv32/ug/#_enabling_risc_v_cpu_extensions[User Guide: Enabling RISC-V CPU Extensions] for more information.
+| _MARCH_           | The targeted RISC-V architecture/ISA. Only `rv32` is supported by the NEORV32. Enable compiler support of optional CPU extension by adding the according extension letter (e.g. `rv32im` for _M_ CPU extension). See https://stnolting.github.io/neorv32/ug/#_enabling_risc_v_cpu_extensions[User Guide: Enabling RISC-V CPU Extensions] for more information.
 | _MABI_            | The default 32-bit integer ABI.
 | _USER_FLAGS_      | Additional flags that will be forwarded to the compiler tools
 | _NEORV32_HOME_    | Relative or absolute path to the NEORV32 project home folder. Adapt this if the makefile/project is not in the project's `sw/example folder`.

docs/userguide/content.adoc

@@ -287,7 +287,7 @@ beginning of this script you will find the `MEMORY` configuration listing the di
 ----
 MEMORY
 {
-  ram  (rwx) : ORIGIN = 0x80000000, LENGTH = DEFINED(make_bootloader) ? 512 : 8*1024 # <1>
+  ram  (rwx) : ORIGIN = 0x80000000, LENGTH = DEFINED(make_bootloader) ? 512 : 8*1024 <1>
 ...
 ----
 <1> Size of the data memory address space (right-most value) (internal/external DMEM); here 8kB
@@ -615,8 +615,8 @@ the `MABI` variable according to your CPU hardware configuration.
 [source,makefile]
 ----
 # CPU architecture and ABI
-MARCH = -march=rv32i # <1>
-MABI = -mabi=ilp32 # <2>
+MARCH ?= rv32i <1>
+MABI  ?= ilp32 <2>
 ----
 <1> MARCH = Machine architecture ("ISA string")
 <2> MABI = Machine binary interface
@@ -641,7 +641,7 @@ You can also override the default `MARCH` and `MABI` configurations from the mak
 
 [source,bash]
 ----
-$ make MARCH=-march=rv32ic clean_all all
+$ make MARCH=rv32ic clean_all all
 ----
 
 [NOTE]
@@ -1180,15 +1180,15 @@ Blinking LED demo program
 
 To do a quick test of the NEORV32 make sure to have https://github.com/ghdl/ghdl[GHDL] and a
 [RISC-V gcc toolchain](https://github.com/stnolting/riscv-gcc-prebuilt) installed.
-Navigate to the project's `sw/example/hello_world` folder and run `make USER_FLAGS+=-DUART0_SIM_MODE MARCH=-march=rv32imac clean_all sim`:
+Navigate to the project's `sw/example/hello_world` folder and run `make USER_FLAGS+=-DUART0_SIM_MODE MARCH=rv32imac clean_all sim`:
 
 [TIP]
 The simulator will output some _sanity check_ notes (and warnings or even errors if something is ill-configured)
 right at the beginning of the simulation to give a brief overview of the actual NEORV32 SoC and CPU configurations.
 
 [source, bash]
 ----
-stnolting@Einstein:/mnt/n/Projects/neorv32/sw/example/hello_world$ make USER_FLAGS+=-DUART0_SIM_MODE MARCH=-march=rv32imac clean_all sim
+stnolting@Einstein:/mnt/n/Projects/neorv32/sw/example/hello_world$ make USER_FLAGS+=-DUART0_SIM_MODE MARCH=rv32imac clean_all sim
 ../../../sw/lib/source/neorv32_uart.c: In function 'neorv32_uart0_setup':
 ../../../sw/lib/source/neorv32_uart.c:301:4: warning: #warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulations only! [-Wcpp]
   301 |   #warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulations only! <1>
@@ -1435,7 +1435,7 @@ Navigate to `sw/example/blink_led` and compile the application:
 .Compile the test application
 [source, bash]
 --------------------------
-.../neorv32/sw/example/blink_led$ make MARCH=-march=rv32i USER_FLAGS+=-g clean_all all
+.../neorv32/sw/example/blink_led$ make MARCH=rv32i USER_FLAGS+=-g clean_all all
 --------------------------
 
 .Adding debug symbols to the executable

sw/common/common.mk

@@ -16,8 +16,8 @@ EFFORT ?= -Os
 RISCV_PREFIX ?= riscv32-unknown-elf-
 
 # CPU architecture and ABI
-MARCH ?= -march=rv32i
-MABI  ?= -mabi=ilp32
+MARCH ?= rv32i
+MABI  ?= ilp32
 
 # User flags for additional configuration (will be added to compiler flags)
 USER_FLAGS ?=
@@ -87,7 +87,7 @@ CC_X86 = g++ -Wall -O -g
 IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
 # Compiler & linker flags
-CC_OPTS  = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
+CC_OPTS  = -march=$(MARCH) -mabi=$(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
 CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
 # This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
 CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4

sw/example/coremark/README.md

@@ -17,7 +17,7 @@ Make sure to define `RUN_COREMARK` *when invoking* `make` (via `USER_FLAGS+=-DRU
 
 To build the executable for a certain CPU configuration and a certain optimization level of the benchmark, type (`rv32imc` and `O3` in this example):
 
-`> make USER_FLAGS+=-DRUN_COREMARK MARCH=-march=rv32imc EFFORT=-O3 clean_all exe`
+`> make USER_FLAGS+=-DRUN_COREMARK MARCH=rv32imc EFFORT=-O3 clean_all exe`
 
 
 # Running

sw/example/demo_freeRTOS/makefile

@@ -53,8 +53,8 @@ EFFORT ?= -Os
 RISCV_PREFIX ?= riscv32-unknown-elf-
 
 # CPU architecture and ABI
-MARCH ?= -march=rv32i
-MABI  ?= -mabi=ilp32
+MARCH ?= rv32i
+MABI  ?= ilp32
 
 # User flags for additional configuration (will be added to compiler flags)
 USER_FLAGS ?=

sw/example/dhrystone/dhrystone.sh

@@ -1 +1 @@
-make USER_FLAGS+=-DRUN_DHRYSTONE USER_FLAGS+=-DDHRY_ITERS=2000000 USER_FLAGS+=-DNOENUM MARCH=-march=rv32imc EFFORT=-O3 clean_all exe
+make USER_FLAGS+=-DRUN_DHRYSTONE USER_FLAGS+=-DDHRY_ITERS=2000000 USER_FLAGS+=-DNOENUM MARCH=rv32imc EFFORT=-O3 clean_all exe

sw/example/floating_point_test/README.md

@@ -8,11 +8,11 @@ defined by the RISC-V `F` single-precision floating-point extension). Hence, the
 * floating-point load/store operations (`FLW`, `FSW`) and their compressed versions
 * integer register file `x` <-> floating point register file `f` move operations (`FMV.W.X`, `FMV.X.W`)
 
-:information_source: More information regarding the RISC-V `Zfinx` single-precision floating-point extension can be found in the officail GitHub repo:
+:information_source: More information regarding the RISC-V `Zfinx` single-precision floating-point extension can be found in the official GitHub repo:
 [`github.com/riscv/riscv-zfinx`](https://github.com/riscv/riscv-zfinx).
 
 :warning: The RISC-V `Zfinx` extension is not officially ratified yet, but it is assumed to remain unchanged. Hence, it is not supported by the upstream RISC-V GCC port.
-Make sure you **do not** use the `f` ISA attribute when compiling applications that use floating-point arithmetic (`-march=rv32i*f*` is **NOT ALLOWED!**).
+Make sure you **do not** use the `f` ISA attribute when compiling applications that use floating-point arithmetic (`MARCH=rv32i*f*` is **NOT ALLOWED!**).
 
 
 ### :warning: FPU Limitations
@@ -32,7 +32,7 @@ For example, the floating-point addition instruction `FADD.S` can be invoked usi
 float riscv_intrinsic_fadds(float rs1, float rs2)
 ```
 
-The pure-software emulation instruction, which uses the standard builtin functions to execute all floating-point operations, is available via wrapper function. The
+The pure-software emulation instruction, which uses the standard built-in functions to execute all floating-point operations, is available via wrapper function. The
 emulation function for the `FADD.S` instruction is:
 
 ```c
@@ -47,6 +47,6 @@ The provided test program `main.c` verifies all currently implemented `Zfinx` in
 
 ## Resources
 
-* Great page with online calculators for floating-point artihmetic: [http://www.ecs.umass.edu/ece/koren/arith/simulator/](http://www.ecs.umass.edu/ece/koren/arith/simulator/)
+* Great page with online calculators for floating-point arithmetic: [http://www.ecs.umass.edu/ece/koren/arith/simulator/](http://www.ecs.umass.edu/ece/koren/arith/simulator/)
 * A handy tool for visualizing floating-point numbers in their binary representation: [https://www.h-schmidt.net/FloatConverter/IEEE754.html](https://www.h-schmidt.net/FloatConverter/IEEE754.html)
 * This helped me to understand what results the different FPU operation generate when having "special" inputs like NaN: [https://techdocs.altium.com/display/FPGA/IEEE+754+Standard+-+Overview](https://techdocs.altium.com/display/FPGA/IEEE+754+Standard+-+Overview)

sw/ocd-firmware/makefile

@@ -55,8 +55,8 @@ EFFORT ?= -Os
 RISCV_PREFIX ?= riscv32-unknown-elf-
 
 # CPU architecture and ABI
-MARCH = -march=rv32i
-MABI  = -mabi=ilp32
+MARCH = rv32i
+MABI  = ilp32
 
 # User flags for additional configuration (will be added to compiler flags)
 USER_FLAGS ?=
@@ -117,7 +117,7 @@ CC_X86 = g++ -Wall -O -g
 IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
 # Compiler & linker flags
-CC_OPTS  = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
+CC_OPTS  = -march=$(MARCH) -mabi=$(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
 CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
 # This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
 CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4