[sw] update TRNG HAL

stnolting · Jun 7, 2024 · c34a3cb · c34a3cb
1 parent 78cc95a
commit c34a3cb
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Showing 4 changed files with 24 additions and 14 deletions.
diff --git a/sw/lib/include/neorv32.h b/sw/lib/include/neorv32.h
@@ -47,6 +47,13 @@ enum NEORV32_CLOCK_PRSC_enum {
  * @name Fast Interrupt Requests (FIRQ) device aliases
  **************************************************************************/
 /**@{*/
+/** @name True-Random Number Generator (TRNG) */
+/**@{*/
+#define TRNG_FIRQ_ENABLE       CSR_MIE_FIRQ0E    /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
+#define TRNG_FIRQ_PENDING      CSR_MIP_FIRQ0P    /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
+#define TRNG_RTE_ID            RTE_TRAP_FIRQ_0   /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
+#define TRNG_TRAP_CODE         TRAP_CODE_FIRQ_0  /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
+/**@}*/
 /** @name Custom Functions Subsystem (CFS) */
 /**@{*/
 #define CFS_FIRQ_ENABLE        CSR_MIE_FIRQ1E    /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */

diff --git a/sw/lib/include/neorv32_trng.h b/sw/lib/include/neorv32_trng.h
@@ -38,6 +38,7 @@ enum NEORV32_TRNG_CTRL_enum {
   TRNG_CTRL_FIFO_LSB        = 16, /**< TRNG data/control register(16) (r/-): log2(FIFO size), LSB */
   TRNG_CTRL_FIFO_MSB        = 19, /**< TRNG data/control register(19) (r/-): log2(FIFO size), MSB */
 
+  TRNG_CTRL_IRQ_SEL         = 27, /**< TRNG data/control register(27) (r/w): Interrupt trigger select (0 = data available, 1 = FIFO full) */
   TRNG_CTRL_FIFO_CLR        = 28, /**< TRNG data/control register(28) (-/w): Clear data FIFO (auto clears) */
   TRNG_CTRL_SIM_MODE        = 29, /**< TRNG data/control register(29) (r/-): PRNG mode (simulation mode) */
   TRNG_CTRL_EN              = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */
@@ -51,7 +52,7 @@ enum NEORV32_TRNG_CTRL_enum {
  **************************************************************************/
 /**@{*/
 int  neorv32_trng_available(void);
-void neorv32_trng_enable(void);
+void neorv32_trng_enable(int irq_sel);
 void neorv32_trng_disable(void);
 void neorv32_trng_fifo_clear(void);
 int  neorv32_trng_get_fifo_depth(void);

diff --git a/sw/lib/source/neorv32_trng.c b/sw/lib/source/neorv32_trng.c
@@ -37,27 +37,24 @@ int neorv32_trng_available(void) {
 
 /**********************************************************************//**
  * Reset, configure and enable TRNG.
+ *
+ * @param[in] irq_sel Interrupt trigger select (0 = data available, 1 = FIFO full).
  **************************************************************************/
-void neorv32_trng_enable(void) {
-
-  int i;
+void neorv32_trng_enable(int irq_sel) {
 
-  NEORV32_TRNG->CTRL = 0; // reset
+  NEORV32_TRNG->CTRL = 0; // disable and reset
 
   // wait for all internal components to reset
+  int i;
   for (i=0; i<256; i++) {
     asm volatile ("nop");
   }
 
-  NEORV32_TRNG->CTRL = 1 << TRNG_CTRL_EN; // activate
-
-  // "warm-up"
-  for (i=0; i<256; i++) {
-    asm volatile ("nop");
-  }
-
-  // flush random data "pool"
-  neorv32_trng_fifo_clear();
+  uint32_t tmp = 0;
+  tmp |= (1 << TRNG_CTRL_EN); // enable
+  tmp |= (((uint32_t)(irq_sel & 1)) << TRNG_CTRL_IRQ_SEL); // interrupt trigger select
+  tmp |= (1 << TRNG_CTRL_FIFO_CLR); // clear data FIFO
+  NEORV32_TRNG->CTRL = tmp;
 }
 
 

diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd
@@ -1341,6 +1341,11 @@
               <access>read-only</access>
               <description>Log2(FIFO size)</description>
             </field>
+            <field>
+              <name>TRNG_CTRL_IRQ_SEL</name>
+              <bitRange>[27:27]</bitRange>
+              <description>Interrupt trigger select (0 = data available, 1 = FIFO full)</description>
+            </field>
             <field>
               <name>TRNG_CTRL_FIFO_CLR</name>
               <bitRange>[28:28]</bitRange>