[rtl] TRNG: add data-available interrupt

stnolting · Jun 7, 2024 · 78cc95a · 78cc95a
1 parent d6d31fc
commit 78cc95a
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Showing 3 changed files with 32 additions and 8 deletions.
diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090906"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090907"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
@@ -318,7 +318,7 @@ architecture neorv32_top_rtl of neorv32_top is
 
   -- IRQs --
   type firq_enum_t is (
-    FIRQ_UART0_RX, FIRQ_UART0_TX, FIRQ_UART1_RX, FIRQ_UART1_TX, FIRQ_SPI, FIRQ_SDI, FIRQ_TWI,
+    FIRQ_TRNG, FIRQ_UART0_RX, FIRQ_UART0_TX, FIRQ_UART1_RX, FIRQ_UART1_TX, FIRQ_SPI, FIRQ_SDI, FIRQ_TWI,
     FIRQ_CFS, FIRQ_NEOLED, FIRQ_XIRQ, FIRQ_GPTMR, FIRQ_ONEWIRE, FIRQ_DMA, FIRQ_SLINK_RX, FIRQ_SLINK_TX
   );
   type firq_t is array (firq_enum_t) of std_ulogic;
@@ -558,7 +558,7 @@ begin
     );
 
     -- fast interrupt requests (FIRQs) --
-    cpu_firq(0)  <= '0'; -- reserved
+    cpu_firq(0)  <= firq(FIRQ_TRNG);
     cpu_firq(1)  <= firq(FIRQ_CFS);
     cpu_firq(2)  <= firq(FIRQ_UART0_RX);
     cpu_firq(3)  <= firq(FIRQ_UART0_TX);
@@ -1391,7 +1391,8 @@ begin
         clk_i     => clk_i,
         rstn_i    => rstn_sys,
         bus_req_i => iodev_req(IODEV_TRNG),
-        bus_rsp_o => iodev_rsp(IODEV_TRNG)
+        bus_rsp_o => iodev_rsp(IODEV_TRNG),
+        irq_o     => firq(FIRQ_TRNG)
       );
     end generate;
 

diff --git a/rtl/core/neorv32_trng.vhd b/rtl/core/neorv32_trng.vhd
@@ -23,7 +23,8 @@ entity neorv32_trng is
     clk_i     : in  std_ulogic; -- global clock line
     rstn_i    : in  std_ulogic; -- global reset line, low-active, async
     bus_req_i : in  bus_req_t;  -- bus request
-    bus_rsp_o : out bus_rsp_t   -- bus response
+    bus_rsp_o : out bus_rsp_t;  -- bus response
+    irq_o     : out std_ulogic  -- data-available interrupt
   );
 end neorv32_trng;
 
@@ -46,6 +47,7 @@ architecture neorv32_trng_rtl of neorv32_trng is
   constant ctrl_fifo_size2_c : natural := 18; -- r/-: log2(FIFO size) bit 2
   constant ctrl_fifo_size3_c : natural := 19; -- r/-: log2(FIFO size) bit 3
   --
+  constant ctrl_irq_sel_c    : natural := 27; -- r/w: interrupt select (0 = data available, 1 = FIFO full)
   constant ctrl_fifo_clr_c   : natural := 28; -- -/w: Clear data FIFO (auto clears)
   constant ctrl_sim_mode_c   : natural := 29; -- r/-: TRNG implemented in pseudo-RNG simulation mode
   constant ctrl_en_c         : natural := 30; -- r/w: TRNG enable
@@ -68,7 +70,7 @@ architecture neorv32_trng_rtl of neorv32_trng is
   end component;
 
   -- control --
-  signal enable, fifo_clr : std_ulogic;
+  signal enable, irq_sel, fifo_clr : std_ulogic;
 
   -- data FIFO --
   type fifo_t is record
@@ -93,8 +95,9 @@ begin
       bus_rsp_o.ack   <= '0';
       bus_rsp_o.err   <= '0';
       bus_rsp_o.data  <= (others => '0');
-      enable          <= '0';
       fifo_clr        <= '0';
+      irq_sel         <= '0';
+      enable          <= '0';
     elsif rising_edge(clk_i) then
       -- defaults --
       bus_rsp_o.ack  <= bus_req_i.stb;
@@ -104,13 +107,15 @@ begin
       -- host access --
       if (bus_req_i.stb = '1') then
         if (bus_req_i.rw = '1') then -- write access
-          enable   <= bus_req_i.data(ctrl_en_c);
+          irq_sel  <= bus_req_i.data(ctrl_irq_sel_c);
           fifo_clr <= bus_req_i.data(ctrl_fifo_clr_c);
+          enable   <= bus_req_i.data(ctrl_en_c);
         else -- read access
           bus_rsp_o.data(ctrl_data_msb_c downto ctrl_data_lsb_c) <= fifo.rdata;
           --
           bus_rsp_o.data(ctrl_fifo_size3_c downto ctrl_fifo_size0_c) <= std_ulogic_vector(to_unsigned(index_size_f(IO_TRNG_FIFO), 4));
           --
+          bus_rsp_o.data(ctrl_irq_sel_c)  <= irq_sel;
           bus_rsp_o.data(ctrl_sim_mode_c) <= bool_to_ulogic_f(sim_mode_c);
           bus_rsp_o.data(ctrl_en_c)       <= enable;
           bus_rsp_o.data(ctrl_valid_c)    <= fifo.avail;
@@ -166,6 +171,24 @@ begin
   fifo.clear <= '1' when (enable = '0') or (fifo_clr = '1') else '0';
   fifo.re    <= '1' when (bus_req_i.stb = '1') and (bus_req_i.rw = '0') else '0';
 
+  -- IRQ generator --
+  irq_generator: process(rstn_i, clk_i)
+  begin
+    if (rstn_i = '0') then
+      irq_o <= '0';
+    elsif rising_edge(clk_i) then
+      if (enable = '1') then
+        if (irq_sel = '0') then -- fire IRQ if any data is available
+          irq_o <= fifo.avail;
+        else -- fire IRQ if data FIFO is full
+          irq_o <= not fifo.free;
+        end if;
+      else
+        irq_o <= '0';
+      end if;
+    end if;
+  end process irq_generator;
+
 
 end neorv32_trng_rtl;