update Radiant project

disable TRNG, decrease PLL clock to 22.125 MHz #143
stnolting · Feb 3, 2024 · f5e7912 · f5e7912
1 parent 2d2fabf
commit f5e7912
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Showing 4 changed files with 20 additions and 21 deletions.
diff --git a/radiant/UPduino_v3/README.md b/radiant/UPduino_v3/README.md
@@ -18,8 +18,8 @@ and a set of standard peripherals like UART, TWI and SPI.
 - [x] NEORV32 version: v1.9.3.9
 - [x] CPU: `rv32imacu_Zicsr_Zicntr` (reduced CPU `[m]instret` & `[m]cycle` counter width!)
 - [x] Memory: 64 kB instruction memory (internal IMEM), 64 kB data memory (internal DMEM), 4 kB bootloader ROM
-- [x] Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`, `TRNG`
-- [x] Clock: 24 MHz from on-chip HF oscillator (via PLL)
+- [x] Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`
+- [x] Clock: 22.125 MHz from on-chip HF oscillator (via PLL)
 - [x] Reset: via PLL "locked" signal; external "reset" via FPGA re-reconfiguration pin (`creset_n`)
 - [x] Tested with processor version [`1.6.1.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
 - [x] On-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader)

diff --git a/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd b/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd
@@ -74,7 +74,7 @@ end neorv32_upduino_v3_top;
 architecture neorv32_upduino_v3_top_rtl of neorv32_upduino_v3_top is
 
   -- configuration --
-  constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz
+  constant f_clock_c : natural := 22125000; -- PLL output clock frequency in Hz
 
   -- On-chip oscillator --
   signal hf_osc_clk : std_logic;
@@ -172,8 +172,7 @@ begin
     IO_SPI_EN                    => true,        -- implement serial peripheral interface (SPI)?
     IO_TWI_EN                    => true,        -- implement two-wire interface (TWI)?
     IO_PWM_NUM_CH                => 3,           -- number of PWM channels to implement (0..60); 0 = disabled
-    IO_WDT_EN                    => true,        -- implement watch dog timer (WDT)?
-    IO_TRNG_EN                   => true         -- implement true random number generator (TRNG)?
+    IO_WDT_EN                    => true         -- implement watch dog timer (WDT)?
   )
   port map (
     -- Global control --

diff --git a/radiant/UPduino_v3/system_pll/rtl/system_pll.v b/radiant/UPduino_v3/system_pll/rtl/system_pll.v
@@ -3,7 +3,7 @@
     Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
     2023.2.0.38.1
     Soft IP Version: 1.0.1
-    2024 01 31 21:49:38
+    2024 02 03 22:46:28
 *******************************************************************************/
 /*******************************************************************************
     Wrapper Module generated per user settings.
@@ -18,21 +18,21 @@ module system_pll (ref_clk_i,
     output lock_o ; 
     output outcore_o ; 
     output outglobal_o ; 
-    system_pll_ipgen_lscc_pll #(.DIVR("0"),
-            .FILTER_RANGE("2"),
+    system_pll_ipgen_lscc_pll #(.DIVR("1"),
+            .FILTER_RANGE("1"),
             .FREQUENCY_PIN_REFERENCECLK("24.000000"),
-            .FEEDBACK_PATH("PHASE_AND_DELAY"),
+            .FEEDBACK_PATH("SIMPLE"),
             .EXTERNAL_DIVIDE_FACTOR("NONE"),
-            .DIVF("0"),
+            .DIVF("58"),
             .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
             .FDA_FEEDBACK("0"),
             .DELAY_PORT_WIDTH(4),
             .SHIFTREG_DIV_MODE("0"),
-            .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
-            .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
+            .PLLOUT_SELECT_PORTA("GENCLK"),
+            .PLLOUT_SELECT_PORTB("GENCLK"),
             .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
             .FDA_RELATIVE("0"),
-            .DIVQ("3"),
+            .DIVQ("5"),
             .ENABLE_ICEGATE_PORTA("0"),
             .ENABLE_ICEGATE_PORTB("0")) lscc_pll_inst (.ref_clk_i(ref_clk_i), 
                 .rst_n_i(rst_n_i), 

diff --git a/radiant/UPduino_v3/system_pll/system_pll.ipx b/radiant/UPduino_v3/system_pll/system_pll.ipx
@@ -1,12 +1,12 @@
 <?xml version="1.0" ?>
-<RadiantModule architecture="iCE40UP" date="2024 01 31 21:49:38" device="iCE40UP5K" gen_platform="Radiant" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
+<RadiantModule architecture="iCE40UP" date="2024 02 03 22:46:28" device="iCE40UP5K" gen_platform="Radiant" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
  <Package>
-  <File modified="2024 01 31 21:49:38" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
-  <File modified="2024 01 31 21:49:38" name="system_pll.cfg" type="cfg"/>
-  <File modified="2024 01 31 21:49:38" name="misc/system_pll_tmpl.v" type="template_verilog"/>
-  <File modified="2024 01 31 21:49:38" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
-  <File modified="2024 01 31 21:49:38" name="rtl/system_pll.v" type="top_level_verilog"/>
-  <File modified="2024 01 31 21:49:38" name="component.xml" type="IP-XACT_component"/>
-  <File modified="2024 01 31 21:49:38" name="design.xml" type="IP-XACT_design"/>
+  <File modified="2024 02 03 22:46:28" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
+  <File modified="2024 02 03 22:46:28" name="system_pll.cfg" type="cfg"/>
+  <File modified="2024 02 03 22:46:28" name="misc/system_pll_tmpl.v" type="template_verilog"/>
+  <File modified="2024 02 03 22:46:28" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
+  <File modified="2024 02 03 22:46:28" name="rtl/system_pll.v" type="top_level_verilog"/>
+  <File modified="2024 02 03 22:46:28" name="component.xml" type="IP-XACT_component"/>
+  <File modified="2024 02 03 22:46:28" name="design.xml" type="IP-XACT_design"/>
  </Package>
 </RadiantModule>