[radiant] update to Radiant 2023.2

#143
stnolting · Jan 31, 2024 · 2d2fabf · 2d2fabf
1 parent 6a66163
commit 2d2fabf
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Showing 3 changed files with 11 additions and 11 deletions.
diff --git a/radiant/UPduino_v3/neorv32_upduino_v3.rdf b/radiant/UPduino_v3/neorv32_upduino_v3.rdf
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<RadiantProject version="4.2" title="neorv32_upduino_v3" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
+<RadiantProject version="4.2" radiant="2023.2.0.38.1" title="neorv32_upduino_v3" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
     <Options/>
     <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="lse" default_strategy="Strategy1">
         <Options def_top="neorv32_upduino_v3_top"/>

diff --git a/radiant/UPduino_v3/system_pll/rtl/system_pll.v b/radiant/UPduino_v3/system_pll/rtl/system_pll.v
@@ -1,9 +1,9 @@
 
 /*******************************************************************************
     Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
-    3.1.1.232.1
+    2023.2.0.38.1
     Soft IP Version: 1.0.1
-    2024 01 31 17:46:53
+    2024 01 31 21:49:38
 *******************************************************************************/
 /*******************************************************************************
     Wrapper Module generated per user settings.

diff --git a/radiant/UPduino_v3/system_pll/system_pll.ipx b/radiant/UPduino_v3/system_pll/system_pll.ipx
@@ -1,12 +1,12 @@
 <?xml version="1.0" ?>
-<RadiantModule architecture="iCE40UP" date="2024 01 31 17:46:53" device="iCE40UP5K" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
+<RadiantModule architecture="iCE40UP" date="2024 01 31 21:49:38" device="iCE40UP5K" gen_platform="Radiant" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
  <Package>
-  <File modified="2024 01 31 17:46:53" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
-  <File modified="2024 01 31 17:46:53" name="system_pll.cfg" type="cfg"/>
-  <File modified="2024 01 31 17:46:53" name="misc/system_pll_tmpl.v" type="template_verilog"/>
-  <File modified="2024 01 31 17:46:53" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
-  <File modified="2024 01 31 17:46:53" name="rtl/system_pll.v" type="top_level_verilog"/>
-  <File modified="2024 01 31 17:46:53" name="component.xml" type="IP-XACT_component"/>
-  <File modified="2024 01 31 17:46:53" name="design.xml" type="IP-XACT_design"/>
+  <File modified="2024 01 31 21:49:38" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
+  <File modified="2024 01 31 21:49:38" name="system_pll.cfg" type="cfg"/>
+  <File modified="2024 01 31 21:49:38" name="misc/system_pll_tmpl.v" type="template_verilog"/>
+  <File modified="2024 01 31 21:49:38" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
+  <File modified="2024 01 31 21:49:38" name="rtl/system_pll.v" type="top_level_verilog"/>
+  <File modified="2024 01 31 21:49:38" name="component.xml" type="IP-XACT_component"/>
+  <File modified="2024 01 31 21:49:38" name="design.xml" type="IP-XACT_design"/>
  </Package>
 </RadiantModule>