[radiant] update Upduino example project

stnolting · Jan 31, 2024 · 6a66163 · 6a66163
1 parent eb4dce7
commit 6a66163
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Showing 4 changed files with 39 additions and 29 deletions.
diff --git a/radiant/UPduino_v3/README.md b/radiant/UPduino_v3/README.md
@@ -15,6 +15,7 @@ and a set of standard peripherals like UART, TWI and SPI.
 
 ### Processor Configuration
 
+- [x] NEORV32 version: v1.9.3.9
 - [x] CPU: `rv32imacu_Zicsr_Zicntr` (reduced CPU `[m]instret` & `[m]cycle` counter width!)
 - [x] Memory: 64 kB instruction memory (internal IMEM), 64 kB data memory (internal DMEM), 4 kB bootloader ROM
 - [x] Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`, `TRNG`

diff --git a/radiant/UPduino_v3/neorv32_upduino_v3.rdf b/radiant/UPduino_v3/neorv32_upduino_v3.rdf
@@ -6,12 +6,12 @@
         <Source name="neorv32_upduino_v3_top.vhd" type="VHDL" type_short="VHDL">
             <Options lib="work" top_module="neorv32_upduino_v3_top"/>
         </Source>
-        <Source name="system_pll/system_pll.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
         <Source name="../../neorv32/rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
+        <Source name="../../neorv32/rtl/core/neorv32_clockgate.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="neorv32"/>
+        </Source>
         <Source name="../../neorv32/rtl/core/neorv32_application_image.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
@@ -153,6 +153,9 @@
         <Source name="../../neorv32/rtl/core/neorv32_top.vhd" type="VHDL" type_short="VHDL">
             <Options lib="neorv32"/>
         </Source>
+        <Source name="system_pll/system_pll.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
         <Source name="neorv32_upduino_v3.pdc" type="Physical Constraints File" type_short="PDC">
             <Options/>
         </Source>

diff --git a/radiant/UPduino_v3/system_pll/rtl/system_pll.v b/radiant/UPduino_v3/system_pll/rtl/system_pll.v
@@ -1,9 +1,9 @@
 
 /*******************************************************************************
     Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
-    2.1.0.27.2
+    3.1.1.232.1
     Soft IP Version: 1.0.1
-    Wed May 12 22:58:47 2021
+    2024 01 31 17:46:53
 *******************************************************************************/
 /*******************************************************************************
     Wrapper Module generated per user settings.
@@ -26,6 +26,7 @@ module system_pll (ref_clk_i,
             .DIVF("0"),
             .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
             .FDA_FEEDBACK("0"),
+            .DELAY_PORT_WIDTH(4),
             .SHIFTREG_DIV_MODE("0"),
             .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
             .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
@@ -36,8 +37,7 @@ module system_pll (ref_clk_i,
             .ENABLE_ICEGATE_PORTB("0")) lscc_pll_inst (.ref_clk_i(ref_clk_i), 
                 .rst_n_i(rst_n_i), 
                 .feedback_i(1'b0), 
-                .dynamic_delay_i({4'b0000,
-                    4'b0000}), 
+                .dynamic_delay_i(4'b0000), 
                 .bypass_i(1'b0), 
                 .latch_i(1'b0), 
                 .lock_o(lock_o), 
@@ -107,6 +107,7 @@ endmodule
 module system_pll_ipgen_lscc_pll #(parameter DIVR = "1", 
         parameter DIVF = "1", 
         parameter DIVQ = "1", 
+        parameter DELAY_PORT_WIDTH = 4, 
         parameter FEEDBACK_PATH = "SIMPLE", 
         parameter FILTER_RANGE = "0", 
         parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED", 
@@ -129,7 +130,7 @@ module system_pll_ipgen_lscc_pll #(parameter DIVR = "1",
     input ref_clk_i, 
     input rst_n_i, 
     input feedback_i, 
-    input [7:0] dynamic_delay_i, 
+    input [(DELAY_PORT_WIDTH - 1):0] dynamic_delay_i, 
     input bypass_i, 
     input latch_i, 
     output wire lock_o, 
@@ -160,22 +161,27 @@ module system_pll_ipgen_lscc_pll #(parameter DIVR = "1",
             end
     endgenerate
     generate
-        if ((DELAY_ADJUSTMENT_MODE_FEEDBACK == "FIXED")) 
+        if (((DELAY_ADJUSTMENT_MODE_FEEDBACK == "FIXED") && (DELAY_ADJUSTMENT_MODE_RELATIVE == "FIXED"))) 
             begin : genblk2
-                assign dynamic_delay_w[3:0] = 4'b0 ; 
+                assign dynamic_delay_w[7:0] = 8'b0 ; 
             end
         else
-            begin : genblk2
-                assign dynamic_delay_w[3:0] = dynamic_delay_i[3:0] ; 
-            end
-        if ((DELAY_ADJUSTMENT_MODE_RELATIVE == "FIXED")) 
-            begin : genblk3
-                assign dynamic_delay_w[7:4] = 4'b0 ; 
-            end
-        else
-            begin : genblk3
-                assign dynamic_delay_w[7:4] = dynamic_delay_i[7:4] ; 
-            end
+            if (((DELAY_ADJUSTMENT_MODE_FEEDBACK == "DYNAMIC") && (DELAY_ADJUSTMENT_MODE_RELATIVE == "DYNAMIC"))) 
+                begin : genblk2
+                    assign dynamic_delay_w[7:0] = dynamic_delay_i[7:0] ; 
+                end
+            else
+                if (((DELAY_ADJUSTMENT_MODE_FEEDBACK == "FIXED") && (DELAY_ADJUSTMENT_MODE_RELATIVE == "DYNAMIC"))) 
+                    begin : genblk2
+                        assign dynamic_delay_w[7:0] = {dynamic_delay_i[3:0],
+                                    4'b0} ; 
+                    end
+                else
+                    begin : genblk2
+                        //(DELAY_ADJUSTMENT_MODE_FEEDBACK == "DYNAMIC" && DELAY_ADJUSTMENT_MODE_RELATIVE == "FIXED")
+                        assign dynamic_delay_w[7:0] = {4'b0,
+                                    dynamic_delay_i[3:0]} ; 
+                    end
     endgenerate
     // -----------------------------------------------------------------------------
     // PLL Primitive Instantiation

diff --git a/radiant/UPduino_v3/system_pll/system_pll.ipx b/radiant/UPduino_v3/system_pll/system_pll.ipx
@@ -1,12 +1,12 @@
 <?xml version="1.0" ?>
-<RadiantModule architecture="iCE40UP" date="2021 05 12 22:58:47" device="iCE40UP5K" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
+<RadiantModule architecture="iCE40UP" date="2024 01 31 17:46:53" device="iCE40UP5K" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
  <Package>
-  <File modified="2021 05 12 22:58:47" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
-  <File modified="2021 05 12 22:58:47" name="system_pll.cfg" type="cfg"/>
-  <File modified="2021 05 12 22:58:47" name="misc/system_pll_tmpl.v" type="template_verilog"/>
-  <File modified="2021 05 12 22:58:47" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
-  <File modified="2021 05 12 22:58:47" name="rtl/system_pll.v" type="top_level_verilog"/>
-  <File modified="2021 05 12 22:58:47" name="component.xml" type="IP-XACT_component"/>
-  <File modified="2021 05 12 22:58:47" name="design.xml" type="IP-XACT_design"/>
+  <File modified="2024 01 31 17:46:53" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
+  <File modified="2024 01 31 17:46:53" name="system_pll.cfg" type="cfg"/>
+  <File modified="2024 01 31 17:46:53" name="misc/system_pll_tmpl.v" type="template_verilog"/>
+  <File modified="2024 01 31 17:46:53" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
+  <File modified="2024 01 31 17:46:53" name="rtl/system_pll.v" type="top_level_verilog"/>
+  <File modified="2024 01 31 17:46:53" name="component.xml" type="IP-XACT_component"/>
+  <File modified="2024 01 31 17:46:53" name="design.xml" type="IP-XACT_design"/>
  </Package>
 </RadiantModule>