Merge pull request #160 from lovelesh-mis/revert-159-main

Revert 159 main
stnolting · Apr 4, 2024 · 1838100 · 1838100
2 parents 90a7855 + 2bfb5bc
commit 1838100
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Showing 5 changed files with 16 additions and 15 deletions.
diff --git a/osflow/synthesis.mk b/osflow/synthesis.mk
@@ -17,7 +17,7 @@ endif
 
 ${IMPL}.json: work-obj08.cf $(NEORV32_VERILOG_ALL)
 	$(YOSYS) $(YOSYSFLAGS) \
-	  -m ghdl -p \
+	  -p \
 	  "$(GHDLSYNTH) $(GHDL_FLAGS) --no-formal $(TOP); \
 	  $(READ_VERILOG) synth_${YOSYSSYNTH} \
 	  -top $(TOP) $(YOSYSPIPE) \

diff --git a/radiant/iCEBreaker/impl_1/iCEBreaker_impl_1.bin b/radiant/iCEBreaker/impl_1/iCEBreaker_impl_1.bin
diff --git a/radiant/iCEBreaker/source/impl_1.xcf b/radiant/iCEBreaker/source/impl_1.xcf
@@ -1,6 +1,6 @@
 <?xml version='1.0' encoding='utf-8' ?>
 <!DOCTYPE		ispXCF	SYSTEM	"IspXCF.dtd" >
-<ispXCF version="R2022.1">
+<ispXCF version="R2023.2">
 	<Comment></Comment>
 	<Chain>
 		<Comm>SPI</Comm>
@@ -18,7 +18,8 @@
 				<BScanVal>0</BScanVal>
 			</Bypass>
 			<File>../../impl_1/iCEBreaker_impl_1.bin</File>
-			<FileTime>03/18/24 09:25:47</FileTime>
+			<FileTime>02/10/24 19:41:19</FileTime>
+			<JedecChecksum>0xB101</JedecChecksum>
 			<MemoryType>External SPI Flash Memory (SPI FLASH)</MemoryType>
 			<Operation>Erase,Program,Verify</Operation>
 			<Option>
@@ -102,6 +103,6 @@
 	<CableOptions>
 		<CableName>USB2</CableName>
 		<PortAdd>FTUSB-0</PortAdd>
-		<USBID>iCEBreaker V1.0e A Location 0000 Serial ibSp9gG5A</USBID>
+		<USBID>iCEBreaker V1.0d A Location 0000 Serial ibT0gbT8A</USBID>
 	</CableOptions>
 </ispXCF>
diff --git a/radiant/iCEBreaker/system_pll/rtl/system_pll.v b/radiant/iCEBreaker/system_pll/rtl/system_pll.v
@@ -1,9 +1,9 @@
 
 /*******************************************************************************
     Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
-    2023.2.0.38.1
+    2022.1.0.52.3
     Soft IP Version: 1.0.1
-    2024 03 16 10:02:06
+    2024 02 11 00:11:50
 *******************************************************************************/
 /*******************************************************************************
     Wrapper Module generated per user settings.
@@ -20,7 +20,7 @@ module system_pll (ref_clk_i,
     output outglobal_o ; 
     system_pll_ipgen_lscc_pll #(.DIVR("0"),
             .FILTER_RANGE("1"),
-            .FREQUENCY_PIN_REFERENCECLK("10.000000"),
+            .FREQUENCY_PIN_REFERENCECLK("12.000000"),
             .FEEDBACK_PATH("SIMPLE"),
             .EXTERNAL_DIVIDE_FACTOR("NONE"),
             .DIVF("63"),

diff --git a/radiant/iCEBreaker/system_pll/system_pll.ipx b/radiant/iCEBreaker/system_pll/system_pll.ipx
@@ -1,12 +1,12 @@
 <?xml version="1.0" ?>
-<RadiantModule architecture="iCE40UP" date="2024 03 16 10:02:06" device="iCE40UP5K" gen_platform="Radiant" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
+<RadiantModule architecture="iCE40UP" date="2024 02 11 00:11:50" device="iCE40UP5K" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
  <Package>
-  <File modified="2024 03 16 10:02:06" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
-  <File modified="2024 03 16 10:02:06" name="system_pll.cfg" type="cfg"/>
-  <File modified="2024 03 16 10:02:06" name="misc/system_pll_tmpl.v" type="template_verilog"/>
-  <File modified="2024 03 16 10:02:06" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
-  <File modified="2024 03 16 10:02:06" name="rtl/system_pll.v" type="top_level_verilog"/>
-  <File modified="2024 03 16 10:02:06" name="component.xml" type="IP-XACT_component"/>
-  <File modified="2024 03 16 10:02:06" name="design.xml" type="IP-XACT_design"/>
+  <File modified="2024 02 11 00:11:50" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
+  <File modified="2024 02 11 00:11:50" name="system_pll.cfg" type="cfg"/>
+  <File modified="2024 02 11 00:11:50" name="misc/system_pll_tmpl.v" type="template_verilog"/>
+  <File modified="2024 02 11 00:11:50" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
+  <File modified="2024 02 11 00:11:50" name="rtl/system_pll.v" type="top_level_verilog"/>
+  <File modified="2024 02 11 00:11:50" name="component.xml" type="IP-XACT_component"/>
+  <File modified="2024 02 11 00:11:50" name="design.xml" type="IP-XACT_design"/>
  </Package>
 </RadiantModule>