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Zmmul is now version 1.0 (ratified) RISC-V ISA Build #115: Pull request #1077 opened by a4lg
July 25, 2023 08:59 4m 38s a4lg:zmmul-version-1.0
a4lg:zmmul-version-1.0
July 25, 2023 08:59 4m 38s
C.XOR is not RV64/RV128 only RISC-V ISA Build #114: Pull request #1076 opened by a4lg
July 25, 2023 04:27 4m 54s a4lg:c-instr-table-xor-fix
a4lg:c-instr-table-xor-fix
July 25, 2023 04:27 4m 54s
Remove Extraneous SLLI/SRLI/SRAI instructions RISC-V ISA Build #113: Pull request #1075 opened by charlie-rivos
July 24, 2023 21:16 5m 31s charlie-rivos:remove_extra_sl_sr
charlie-rivos:remove_extra_sl_sr
July 24, 2023 21:16 5m 31s
RISC-V ISA Build RISC-V ISA Build #112: Manually run by wmat
July 24, 2023 15:11 5m 55s main
main
July 24, 2023 15:11 5m 55s
priv-1.13: clarify that MXLEN >= SXLEN; constrain SXLEN >= UXLEN (#1028) RISC-V ISA Build #111: Commit 0d7621d pushed by aswaterman
July 21, 2023 23:03 5m 21s main
main
July 21, 2023 23:03 5m 21s
Merge pull request #1074 from charlie-rivos/typo_in_cs RISC-V ISA Build #110: Commit 2232022 pushed by aswaterman
July 21, 2023 23:02 4m 12s main
main
July 21, 2023 23:02 4m 12s
Resolve incorrect formatting in CS format RISC-V ISA Build #109: Pull request #1074 opened by charlie-rivos
July 21, 2023 22:54 5m 46s charlie-rivos:typo_in_cs
charlie-rivos:typo_in_cs
July 21, 2023 22:54 5m 46s
Merge pull request #1072 from charlie-rivos/fix_integer_register_imme… RISC-V ISA Build #108: Commit 614ebd6 pushed by aswaterman
July 21, 2023 22:50 4m 15s main
main
July 21, 2023 22:50 4m 15s
Merge pull request #1073 from charlie-rivos/correct_amo_register_name RISC-V ISA Build #107: Commit 1e05b63 pushed by aswaterman
July 21, 2023 22:48 5m 6s main
main
July 21, 2023 22:48 5m 6s
Correct Name of LR/SC Instructions rl bit RISC-V ISA Build #106: Pull request #1073 opened by charlie-rivos
July 21, 2023 20:25 4m 42s charlie-rivos:correct_amo_register_name
charlie-rivos:correct_amo_register_name
July 21, 2023 20:25 4m 42s
Make "Integer Register-Immediate Operations" Consistent RISC-V ISA Build #105: Pull request #1072 opened by charlie-rivos
July 21, 2023 19:03 4m 55s charlie-rivos:fix_integer_register_immediate_operations
charlie-rivos:fix_integer_register_immediate_operations
July 21, 2023 19:03 4m 55s
Merge pull request #1071 from charlie-rivos/fix_conditional_branch_bits RISC-V ISA Build #104: Commit 2d166dc pushed by aswaterman
July 21, 2023 04:20 5m 40s main
main
July 21, 2023 04:20 5m 40s
Make "Conditional Branches" wavdrom consistent RISC-V ISA Build #103: Pull request #1071 opened by charlie-rivos
July 21, 2023 04:19 4m 27s charlie-rivos:fix_conditional_branch_bits
charlie-rivos:fix_conditional_branch_bits
July 21, 2023 04:19 4m 27s
Changed VSXLEN to VSXLEN-1 RISC-V ISA Build #102: Commit 546edec pushed by wmat
July 18, 2023 15:10 4m 8s main
main
July 18, 2023 15:10 4m 8s
Changed VSXLEN to VSXLEN-1 RISC-V ISA Build #101: Commit a2cca46 pushed by wmat
July 18, 2023 15:09 4m 15s main
main
July 18, 2023 15:09 4m 15s
Fixing table 27 formatting. RISC-V ISA Build #100: Commit b623b5f pushed by wmat
July 18, 2023 14:41 5m 16s main
main
July 18, 2023 14:41 5m 16s
Fixing table formatting RISC-V ISA Build #99: Commit aefd35b pushed by wmat
July 18, 2023 14:00 4m 29s main
main
July 18, 2023 14:00 4m 29s
Merge pull request #1069 from tariqkurd-repo/patch-5 RISC-V ISA Build #98: Commit cb6e9d3 pushed by wmat
July 18, 2023 13:06 5m 36s main
main
July 18, 2023 13:06 5m 36s
fix formatting RISC-V ISA Build #97: Pull request #1069 synchronize by wmat
July 18, 2023 12:18 4m 6s tariqkurd-repo:patch-5
tariqkurd-repo:patch-5
July 18, 2023 12:18 4m 6s
fix formatting RISC-V ISA Build #96: Pull request #1069 opened by tariqkurd-repo
July 18, 2023 08:27 4m 23s tariqkurd-repo:patch-5
tariqkurd-repo:patch-5
July 18, 2023 08:27 4m 23s
Reformat Table 12 to match LaTeX RISC-V ISA Build #95: Commit 160d53f pushed by wmat
July 17, 2023 14:53 5m 59s main
main
July 17, 2023 14:53 5m 59s
Renamed diagram file. RISC-V ISA Build #94: Commit b099e35 pushed by wmat
July 13, 2023 15:27 4m 58s main
main
July 13, 2023 15:27 4m 58s
Fix SP Load & Store for F Extension RISC-V ISA Build #93: Commit 261384e pushed by wmat
July 13, 2023 15:20 3m 39s main
main
July 13, 2023 15:20 3m 39s
FLW/FSW should have width=S not width=H RISC-V ISA Build #92: Pull request #1067 opened by tariqkurd-repo
July 13, 2023 13:42 5m 5s tariqkurd-repo:patch-4
tariqkurd-repo:patch-4
July 13, 2023 13:42 5m 5s
Files should end in a newline RISC-V ISA Build #91: Commit 71ac43e pushed by aswaterman
July 12, 2023 20:40 4m 15s main
main
July 12, 2023 20:40 4m 15s
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