Compiling
The compilation phase is essentially checking the integrity of the block diagram and setting it up for simulation.
As blocks and wires are created they are added to lists with the Simulation object.
In this phase we assign consecutive integers (starting at zero) to all the blocks,
and to all the wires. This is the .id attribute of those objects. This is used to
create the default names of blocks and wires which can be overriden by supplying a
name= argument to the block or wire constructor.
A subsystem block is effectively replaced with a copy of the blocks that define the subsystem. The blocks are all renamed to the name of the parent block dot the name of the block within the system. The same subsystem can be instantiated multiple times because the original blocks are copied on every instantiation.
The result is one large non-hierarchical wireless.
The inputs and outputs of every block are checked.
- unconnected outputs result in a warning
- unnconnected inputs result in an error since it will never be possible to evaluate the outputs of the block
- an input connected to more than one output is an error
Port values are checked against the number of input and output ports for a block and will generate an error if out of bounds.
A block diagram is a directed graph that may contain cycles. Cycles cannot include leaf nodes (Sink or Source subclasses). A cycle is only problematic if it comprises only Function subclass blocks since it is not possible to evaluate the values on the wires without iteration. A stateful block (Transfer subclass) which is proper, ie. has no direct "pass through" will break this kind of problematic cycle.
bdsim does not attempt iteration. It uses depth-first search from each Function subclass block to identify problematic cycles and raises an error.
When executing a block diagram, a block cannot be evaluated until its input values have been computed. To achieve this an execution plan is created, essentially a dataflow graph. All blocks in the first column are evaluated first (sources and stateful blocks), then the second column and so on.
The dataflow graph can be displayed in a simple tabular format
bd.plan_print()
or saved in GraphViz format
bd.plan_dotfile('myfile.dot')
and converted to any graphical format using dot, for example to render as a PDF file
% dot -Tpdf myfile.dot > myfile.pdf