Manta v1.0.1. This release contains a few improvements, including:
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Bumping to the freshly-released Amaranth 0.5. This has a few implications:
- Generating True-Dual-Port RAMs on Xilinx/AMD platforms no longer results in an
Unrecognized RAM templateerror from Vivado during synthesis. This makes the bidirectional memory core work properly on these devices. - The simulation testbenches have been migrated to to the new async simulation API.
- A few small changes to the HDL were required (
Signal.resetwas replaced withSignal.init, for instance).
- Generating True-Dual-Port RAMs on Xilinx/AMD platforms no longer results in an
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CSV exports of logic analyzer captures. This feature had been in the codebase for some time, but just had never been broken out to the CLI. Now it has!
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Some minor updates to the documentation.