v1.0.1

Manta v1.0.1. This release contains a few improvements, including:

• Bumping to the freshly-released Amaranth 0.5. This has a few implications:

  • Generating True-Dual-Port RAMs on Xilinx/AMD platforms no longer results in an Unrecognized RAM template error from Vivado during synthesis. This makes the bidirectional memory core work properly on these devices.
  • The simulation testbenches have been migrated to to the new async simulation API.
  • A few small changes to the HDL were required (Signal.reset was replaced with Signal.init, for instance).

• CSV exports of logic analyzer captures. This feature had been in the codebase for some time, but just had never been broken out to the CLI. Now it has!

• Some minor updates to the documentation.

v1.0.0

Manta v1.0.0. This release is the first version written in Amaranth HDL! This includes a number of improvements, which I've reproduced below from PR #16:

Improvements for Users:

• Generated Verilog is now truly Verilog-2001 compatible. Some components of the previous RTL (mostly the use of packed/unpacked arrays) were giving synthesis tools trouble. This broke the Logic Analyzer and Memory cores when using Yosys+NextPNR on the ice40, and also required Vivado to load files with the -sv option.
• Switched from MAC to UDP support in EthernetInterface. This is done with the excellent LiteEth project. This does make nMigen a dependency, but we'll see if Amaranth SoC ports it to Amaranth in the future. This also removes Scapy as a dependency, and the builtin Python sockets module is used instead.
• Added host_to_fpga and fpga_to_host modes for the Memory Core. This supports chips that don't have True Dual Port RAMs, most notably the ice40.
• Renamed the BlockMemoryCore to MemoryCore, to reflect the fact that the EDA tools might not choose block memory for a given FPGA. In fact, the FPGA might not even have block memory onboard!
• Fix Logic Analyzer capture modes, immediate and incremental modes are now fully supported on all platforms.
• Comissioned custom ASCII art for the manta version command.

Improvements for Developers:

• No more Verilog templates!
• Added hardware-in-the-loop tests to the test suite. Each commit is now automatically tested on hardware, instead of just having the generated code built with the tools.
• Switched functional simulation from Icarus Verilog to Amaranth's built-in simulator. This is one less tool for developers to install.
• Moved tests from Makefile targets to Pytest. This greatly improves the signal-to-noise ratio of the terminal output when running tests.
• Python imports are now absolute, not relative. This is at the recommendation of Google's Python style guide.
• Moved testing into a Python venv, for more reproducible environments.
• Diagrams are now embedded draw.io SVG files. This should help with image scaling and editing.
• Added more docstrings and marked private methods with underscores.
• Added class for Manta's internal bus, and an abstract base class for Manta's cores. This should make it easier for more cores to be developed in the future.

What about using Manta in Amaranth designs natively?

Unfortunately, we're not quite there yet. That'll hopefully be included in the next release, but the ergonomics of using it in Amaranth need to be baked out more fully.

v0.1.0

Manta v0.1.0. This release is the the last version of the code before the rewrite in Amaranth HDL.