The purpose of the project is the design for FPGA of a Universal Asynchronous Receiver Transmitter that allows the serial transmission/reception data of 8 bits at 9600 bauds. For this purpose, it is required the design in VHDL of a transmitter and receiver module. The functionality of the UART must be validated by means of the corresponding functional simulation, designing the appropriate test bench.
"UART.vhd": Logic of the project
"Prueba_transmisor.vhd": Test bench of the project
To get started you will need to download ISE DS 14.7, whose link can be found in Prerequisites.
See Deployment to know how to deploy the project.
Download and install ISE DS 14.7
The functionality of the UART must be validated by means of a test bench. You can find it in the file "Prueba_transmisor.vhd"
Download the project and open it in ISE DS 14.7 by clicking "File" > "Open Project"
- ISE DS 14.7 - software use for development
- David Párraga - Development - davidParraga
These files are not licensed
⌨️ with ❤️ by davidParraga