-
Notifications
You must be signed in to change notification settings - Fork 0
/
UART.par
190 lines (122 loc) · 6.82 KB
/
UART.par
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
DESKTOP-2LJ8TF9:: Tue Jul 09 08:51:17 2019
par -w -intstyle ise -ol high -t 1 UART_map.ncd UART.ncd UART.pcf
Constraints file: UART.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"UART" is an NCD, version 3.2, device xc3s400, package ft256, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.39 2013-10-13".
Device Utilization Summary:
Number of BUFGMUXs 1 out of 8 12%
Number of External IOBs 23 out of 173 13%
Number of LOCed IOBs 0 out of 23 0%
Number of Slices 51 out of 3584 1%
Number of SLICEMs 0 out of 1792 0%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
Starting Placer
Total REAL time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:adc) REAL time: 1 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:adc) REAL time: 1 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:adc) REAL time: 1 secs
Phase 4.2 Initial Clock and IO Placement
.........
Phase 4.2 Initial Clock and IO Placement (Checksum:38609cb4) REAL time: 1 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:38609cb4) REAL time: 1 secs
Phase 6.3 Local Placement Optimization
.........
Phase 6.3 Local Placement Optimization (Checksum:39738777) REAL time: 1 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:39738777) REAL time: 1 secs
Phase 8.8 Global Placement
..
..
..
..
..
Phase 8.8 Global Placement (Checksum:667a34b9) REAL time: 2 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:667a34b9) REAL time: 2 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:64bf64df) REAL time: 2 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:64bf64df) REAL time: 2 secs
Total REAL time to Placer completion: 2 secs
Total CPU time to Placer completion: 2 secs
Writing design to file UART.ncd
Starting Router
Phase 1 : 343 unrouted; REAL time: 2 secs
Phase 2 : 302 unrouted; REAL time: 2 secs
Phase 3 : 54 unrouted; REAL time: 2 secs
Phase 4 : 66 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Updating file: UART.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion: 3 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_BUFGP | BUFGMUX0| No | 40 | 0.020 | 1.034 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 6.251ns| N/A| 0
_BUFGP | HOLD | 0.799ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 3 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 4419 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file UART.ncd
PAR done!