Commits on Mar 16, 2021

1. Fix issue where inlined cvt could cause crash …

   Due to inlining of Boolean expressions, the following circuit is handled
   directly by the VerilogEmitter:
   
   input a: UInt<4>
   input b: SInt<1>
   output o: UInt<5>
   o <= dshl(a, asUInt(cvt(b)))
   
   Priot to this change, this could crash due to mishandling of cvt in the
   logic to inject parentheses based on Verilog precedence rules.
   
   This is a corner case, but similar bugs would drop up if we open up the
   VerilogEmitter to more expression inlining.

   

   jackkoenig committed Mar 16, 2021
   Configuration menu

   • View commit details
   • Copy full SHA for 1e95e42
   • Browse repository at this point

   Copy the full SHA

   1e95e42 View commit details

   Browse the repository at this point in the history