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Fix issue where inlined cvt could cause crash #2124
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| * These PrimOps emit either {..., a0, ...} or a0 so they never need parentheses | ||
| */ | ||
| private val neverParens: PrimOp => Boolean = | ||
| Set(Shl, Cat, Cvt, AsUInt, AsSInt, AsClock, AsAsyncReset) |
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What about adding Pad? I doubt this case gets hit in any code given the current inlining status, but it looks like it might be possible to get ({a0}) if you got the right tree in the emitter.
Due to inlining of Boolean expressions, the following circuit is handled directly by the VerilogEmitter: input a: UInt<4> input b: SInt<1> output o: UInt<5> o <= dshl(a, asUInt(cvt(b))) Priot to this change, this could crash due to mishandling of cvt in the logic to inject parentheses based on Verilog precedence rules. This is a corner case, but similar bugs would drop up if we open up the VerilogEmitter to more expression inlining.
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Due to inlining of Boolean expressions, the following circuit is handled directly by the VerilogEmitter: input a: UInt<4> input b: SInt<1> output o: UInt<5> o <= dshl(a, asUInt(cvt(b))) Priot to this change, this could crash due to mishandling of cvt in the logic to inject parentheses based on Verilog precedence rules. This is a corner case, but similar bugs would drop up if we open up the VerilogEmitter to more expression inlining. (cherry picked from commit 94d1bee)
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Due to inlining of Boolean expressions, the following circuit is handled directly by the VerilogEmitter: input a: UInt<4> input b: SInt<1> output o: UInt<5> o <= dshl(a, asUInt(cvt(b))) Priot to this change, this could crash due to mishandling of cvt in the logic to inject parentheses based on Verilog precedence rules. This is a corner case, but similar bugs would drop up if we open up the VerilogEmitter to more expression inlining. (cherry picked from commit 94d1bee) Co-authored-by: Jack Koenig <koenig@sifive.com>
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Due to inlining of Boolean expressions, the following circuit is handled
directly by the VerilogEmitter:
Priot to this change, this could crash due to mishandling of cvt in the
logic to inject parentheses based on Verilog precedence rules.
This is a corner case, but similar bugs would drop up if we open up the
VerilogEmitter to more expression inlining.
I considered instead changing
Legalizeto removecvt(that that's perhaps still a good idea), but I wanted to solve a potential class of future issues and, as far as I can tell, this exact case is the only way to hit this bug currently.Fixes #2035 h/t @drom for finding this issue
Contributor Checklist
Type of Improvement
API Impact
No impact
Backend Code Generation Impact
No impact
Desired Merge Strategy
Release Notes
Fix corner case where
cvtof a 1-bitSInt(a no op) could crash the VerilogEmitter if passed as an argument to the shift amount indshlReviewer Checklist (only modified by reviewer)
Please Merge?