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ChangeLog since 3.0 rc3
aquynh edited this page Nov 18, 2014
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18 revisions
Get the latest code from our next branch at https://github.com/aquynh/capstone
PPC:
- Do not print a dot in front of absolute address.
- Fix MR instruction.
Sparc:
- Add missing ICC/XCC registers in operands[] for some alias instructions.
- Print absolute address for Bxx & CALL instructions (rather than relative address).
ARM:
- New field mem_barrier in cs_arm struct.
- Support new mode CS_MODE_V8 for Armv8 A32 encodings. (see this commit)
- Print floating point number in %e format.
- Print some special registers in lowercase (so to be consistent)
- Print immediate in positive form for AND/ORR/EOR/BIC instructions
Mips:
- Fix J/JAL target address calculation.
- Handle Mips32R6 mode properly.
- Fix some Mips64 instructions.
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CS_MODE_MIPS32R6 is now the independent mode (see this commit), so there is no need to combine with CS_MODE_32 anymore (like
CS_MODE_32+CS_MODE_MIPS32R6
), but rather simple like below:
cs_open(CS_ARCH_MIPS, CS_MODE_MIPS32R6);
- new modes CS_MODE_MIPS32 & CS_MODE_MIPS64 to use with Mips (instead of CS_MODE_32 & CS_MODE_64). however, these 2 new modes are aliases of CS_MODE_32 & CS_MODE_64, no old code is broken. however, old code should be modified to use new modes, like in this commit
Arm64:
- ADRP print out absolute address (instead of relative offset).
- imm field of cs_arm64_op has type int64_t (instead of int32_t)
- Print shifter in decimal mode. This is to be consistent with ARM engine
- Add missing commas in SBFIZ/UBFIZ/SBFX/UBFX instructions
- print immediate in hexa for binary bitwise arith instructions: AND/ORR/EOR/TST.
X86: More friendly output for some instructions.
-
RET imm16
always prints out positive number. - Always print out immediate as positive number for AND/OR/XOR.
- Print number in positive form in memory reference address.
- Fix CRC32 instruction.
- Handle 3DNow instruction FEMMS.
- More friendly disassembly for JMP16i (in the form segment:offset)