ChangeLog 3.0.1 RC2

This is the changelog for version 3.0.1-rc2. (Look here for the detailed changelog of v3.0.1-rc1)

NOTE: changes are listed in time order: newer changes are at the top, older changes are at the bottom.

Arm64:

• BL & BLR instructions do not read SP register.

Arm:

• Instructions ADC & SBC do not update flags.

X86:

• Properly handle LOCK, REP, REPE & REPNE prefixes.

Python:

• Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
• Fixed a memory leak for Cython disasm functions when we immaturely quit the enumeration of disassembled instructions.