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ChangeLog 3.0.1 RC2
Nguyen Anh Quynh edited this page Jan 20, 2015
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This is the changelog for version 3.0.1-rc2. (Look here for the detailed changelog of v3.0.1-rc1)
NOTE: changes are listed in time order: newer changes are at the top, older changes are at the bottom.
Arm64:
- BL & BLR instructions do not read SP register.
Arm:
- Instructions ADC & SBC do not update flags.
X86:
- Properly handle LOCK, REP, REPE & REPNE prefixes.
Python:
- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
- Fixed a memory leak for Cython disasm functions when we immaturely quit the enumeration of disassembled instructions.