Commits on Jun 20, 2023

1. riscv64: Implement SIMD icmp …

   These are implemented as a combination of two steps, mask generation and
   mask expansion. Our comparision rules only return their results as a mask
   register, so we need to expand the mask into lane sized elements.
   
   We have 20 (!) comparision instructions, nearly the full table of all IntCC codes
   in VV, VX and VI formats. However there are some holes in this table.
   
   They are:
   * `vmsltu.vi`
   * `vmslt.vi`
   * `vmsgtu.vv`
   * `vmsgt.vv`
   * `vmsgeu.*`
   * `vmsge.*`
   
   Most of these can be replaces with the inverted IntCC instruction, however
   this commit only implements the existing instructions without any inversion
   and the inverted VV versions of `sgtu`/`sgt`/`sgeu`/`sge` since we need them
   to get the full icmp functionality.
   
   I've split the actual mask expansion into it's own separate rule since we are
   going to need it for the `fcmp` rules as well.
   
   The instruction selection for `icmp` is on a separate rule simply because the
   rulse end up less verbose than if they were inlined directly into the `icmp` rule.

   

   afonso360 committed Jun 20, 2023
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