riscv64: Implement SIMD icmp
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These are implemented as a combination of two steps, mask generation and mask expansion. Our comparision rules only return their results as a mask register, so we need to expand the mask into lane sized elements. We have 20 (!) comparision instructions, nearly the full table of all IntCC codes in VV, VX and VI formats. However there are some holes in this table. They are: * `vmsltu.vi` * `vmslt.vi` * `vmsgtu.vv` * `vmsgt.vv` * `vmsgeu.*` * `vmsge.*` Most of these can be replaces with the inverted IntCC instruction, however this commit only implements the existing instructions without any inversion and the inverted VV versions of `sgtu`/`sgt`/`sgeu`/`sge` since we need them to get the full icmp functionality. I've split the actual mask expansion into it's own separate rule since we are going to need it for the `fcmp` rules as well. The instruction selection for `icmp` is on a separate rule simply because the rulse end up less verbose than if they were inlined directly into the `icmp` rule.
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👋 Hey,
This PR Implements SIMD
icmpfor RISC-V. These rules are implemented as a combination of two steps, mask generation and mask expansion. Our comparison rules only return their results as a mask register, so we need to expand the mask into lane sized elements.We have 20 (!) comparison instructions, nearly the full table of all IntCC codes in VV, VX and VI formats. However there are some holes in this table.
They are:
vmsltu.vi(Less than Unsigned (Vec-Imm))vmslt.vi(Less than (Vec-Imm))vmsgtu.vv(Greater than Unsigned (Vec-Vec))vmsgt.vv(Greater than (Vec-Vec))vmsgeu.*(Greater than or equal Unsigned (All formats))vmsge.*(Greater than or equal (All formats))Most of these can be replaced with the inverted IntCC instruction. To minimize the size of this initial PR I've only implemented rules for the opcodes that we have a direct translation.
However, in order to get all IntCC's working I've implemented some of the inverted instruction which are
vmsgtu.vv,vmsgt.vv,vmsgeu.vv,vmsge.vv. These are implemented as alias to their inverted counterparts (with the inputs swapped).I'm planning on adding a follow up commit with the rest of the VX and VI rules in both the LHS an RHS sides. We should end up with 5 rules per IntCC once this is all done.
I've split the actual mask expansion into it's own separate rule since we are going to need it for the
fcmprules as well.The instruction selection for
icmpis on a separate rule simply because the rules end up less verbose than if they were inlined directly into theicmprule.