riscv64: Add .vx format opcodes
#6367
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afonso360
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May 10, 2023
| @@ -840,7 +849,6 @@ pub fn reg_name(reg: Reg) -> String { | |||
| pub fn vec_reg_name(reg: Reg) -> String { | |||
| match reg.to_real_reg() { | |||
| Some(real) => { | |||
| assert_eq!(real.class(), RegClass::Float); | |||
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This assert triggers since we are now trying to format some integer registers and I didn't change the pretty printer. However this function gets removed in #6366, so I figured it's easier to wait for that to be merged and rebase this.
elliottt
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May 11, 2023
elliottt
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May 11, 2023
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👋 Hey,
This PR introduces
.vxformat opcodes, thesesplatan X or F register and perform the respective operation.I've only added
vadd,vsubandvrsub, but these are available for most opcodes.Additionally with the addition of
inegwe now pass thesimd_*_arith.wasttest suites 🎉 . I'm planning on enabling those when both this and the RegClass PR's are merged.