riscv64: Refactor Inst RegClass asserts

bytecodealliance · May 16, 2023 · d905232 · d905232
1 parent 6a5e40e
commit d905232
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Showing 2 changed files with 17 additions and 13 deletions.
diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -4,7 +4,7 @@
 #![allow(dead_code)]
 #![allow(non_camel_case_types)]
 
-use super::lower::isle::generated_code::{VecAMode, VecElementWidth, VecOpCategory};
+use super::lower::isle::generated_code::{VecAMode, VecElementWidth};
 use crate::binemit::{Addend, CodeOffset, Reloc};
 pub use crate::ir::condcodes::IntCC;
 use crate::ir::types::{self, F32, F64, I128, I16, I32, I64, I8, I8X16, R32, R64};
@@ -627,25 +627,18 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
         &Inst::VecAluRRR {
             op, vd, vs1, vs2, ..
         } => {
+            debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
             debug_assert_eq!(vs2.class(), RegClass::Vector);
-            match op.category() {
-                VecOpCategory::OPIVV | VecOpCategory::OPFVV | VecOpCategory::OPMVV => {
-                    debug_assert_eq!(vs1.class(), RegClass::Vector);
-                }
-                VecOpCategory::OPIVX | VecOpCategory::OPMVX => {
-                    debug_assert_eq!(vs1.class(), RegClass::Int);
-                }
-                VecOpCategory::OPFVF => {
-                    debug_assert_eq!(vs1.class(), RegClass::Float);
-                }
-                _ => unreachable!(),
-            }
+            debug_assert_eq!(vs1.class(), op.vs1_regclass());
 
             collector.reg_use(vs1);
             collector.reg_use(vs2);
             collector.reg_def(vd);
         }
         &Inst::VecAluRRImm5 { vd, vs2, .. } => {
+            debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
+            debug_assert_eq!(vs2.class(), RegClass::Vector);
+
             collector.reg_use(vs2);
             collector.reg_def(vd);
         }

diff --git a/cranelift/codegen/src/isa/riscv64/inst/vector.rs b/cranelift/codegen/src/isa/riscv64/inst/vector.rs
@@ -4,6 +4,7 @@ use crate::isa::riscv64::lower::isle::generated_code::{
     VecAMode, VecAluOpRRImm5, VecAluOpRRR, VecAvl, VecElementWidth, VecLmul, VecMaskMode,
     VecOpCategory, VecOpMasking, VecTailMode,
 };
+use crate::machinst::RegClass;
 use crate::Reg;
 use core::fmt;
 
@@ -277,6 +278,16 @@ impl VecAluOpRRR {
             }
         }
     }
+
+    // vs1 is the only variable source, vs2 is fixed.
+    pub fn vs1_regclass(&self) -> RegClass {
+        match self.category() {
+            VecOpCategory::OPIVV | VecOpCategory::OPFVV | VecOpCategory::OPMVV => RegClass::Vector,
+            VecOpCategory::OPIVX | VecOpCategory::OPMVX => RegClass::Int,
+            VecOpCategory::OPFVF => RegClass::Float,
+            _ => unreachable!(),
+        }
+    }
 }
 
 impl fmt::Display for VecAluOpRRR {