ALU32_7nmFinFET

Design Compiler : Logic Synthesis

ALU.v : Verilog Implementation
alu32_mapped.v : Gate level netlist
area.rpt : Area Report
timing.rpt : Timing report
qor.rpt : qor report
Schematic.pdf : Schematic of design

Formality: Logic Equivalence Check (LEC) Golden Netlist vs Implemented Netlist

alu.pdf : Refrencence Container Schematic
alu_mapped.pdf : Implemented Container Schematic

Place & Route: Innovus

standardcells.png : Standard cell sitting of rows
design.png : Optimized design with PG nets