Verilog implementation of SAP-1 computer architecture
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Albert Paul Malvino The architecture is 8 bits and comprises of 16 X 8 memory i.e. 16 memory location with 8 bits in each location. SAP can only perform addition and subtraction and no logical operation. These arithmetic operations are performed by an adder/subtractor unit. There is one general purpose register (B register) used to hold one operand of the arithmetic operation while another is kept by the accumulator register of the SAP-1. In addition, there are 8 LEDs which work as output unit and connected with the 8 bit output register.Here i connected the output to a seven segment display.
All timely moment of data or activities are performed by the control unit This computer is NOT TURING COMPLETE.It has only 5 instructions(LDA,ADD,SUB,OUT,HLT).
for more info: Digital Computer Electronics by Albert Paul Malvino & Jerald A. Brown.
https://www.youtube.com/watch?v=HyznrdDSSGM&list=PLowKtXNTBypGqImE405J2565dvjafglHU