This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART. Please refer to ug871-vivado-high-level-synthesis-tutorial.pdf (Chapter 10)
Instead of DDR test, a more practical project for matrix multiplication application can be found here. Compared with the DDR test, the project implements a practical project for Matrix Multiplication, including data generation, FPGA acceleration and result checking.
If this blog is useful for you, a STAR will be encouragement to me. LOL
VivadoHLS part:
- Please firsr import the HLS project via VivadoHLS (ddr_hls_test)
- Synthesis it and export it as IP
Vivado part:
- Please import the Vivado project (zedboard-base-master)
- Add IP repository which includes the exported HLS IP and refresh IP catalog
- Generated the bitstream and export the hardware to local project
- Launch SDK via Vivado
Xilinx SDK part:
- please refer to ug871-vivado-high-level-synthesis-tutorial.pdf (Chapter 10)
- you can find the source code for Cortex A9 in the directory (/zedboard-base-master/zedboard_base.xpr/zedboard_base/zedboard_base.sdk/test2/src)