Merge pull request YosysHQ#263 from yrabbit/gw1n-9c-pclk

HCLK. Primary clock pins
yrabbit · Aug 13, 2024 · 1c507c2 · 1c507c2
2 parents 9250ce6 + 40d4497
commit 1c507c2
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/apycula/chipdb.py b/apycula/chipdb.py
@@ -1195,6 +1195,13 @@ def fse_create_hclk_nodes(dev, device, fse, dat: Datfile):
                 # strange GW1N-9C input-input aliases
                 for i in {0, 2}:
                     dev.nodes.setdefault(f'X{col}Y{row}/HCLK9-{i}', ('HCLK', {(row, col, f'HCLK_IN{i}')}))[1].add((row, col, f'HCLK_9IN{i}'))
+                # GW1N-9C clock pin aliases
+                if side != 'B': # it’s still unclear on this side, but the
+                                # Tangnano9k external clock is not connected here, so we
+                                # won’t run into problems anytime soon
+                    for i in range(2):
+                        add_node(dev, f'PCLK{side}{i}', "HCLK", row, col, f'LWSPINET{side}{i + 1}');
+
 
             for i in range(4):
                 hnam = f'HCLK_OUT{i}'