This repository contains the TL-Verilog design for a CPU Core implementing the RISC-V R32I ISA. If you want to build your own core, checkout this course.
TL-Verilog (Transaction-Level Verilog) is a HDL, which implements an abstraction layer on top of Verilog. To learn more, checkout their website.
- Go to Makerchip
- Create a new project
- Copy/paste the content of
core.tlv
- Compile/Sim