The aim of this repository is to integrate rvmyth (RISC-V CPU core developed by VSD) with a PLL (Phase Locked Loop) as a clock multiplier using open-source EDA tools. The whole project focuses on Mixed Signal Physical Design.
iverilog and gtkwave
Integration of rvmyth with avsd_pll_1v8.
Install iverilog and gtkwave
The rvmyth is a digital block whereas the pll is an ananlog block. To achieve the integration firstly we need to generate a verilog block for the PLL and take the output of the PLL and give it as an input to the rvmyth. This will create the interface then the PNR flow must be implemented.
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Simulate rvmyth using the following steps:
git clone https://github.com/kunalg123/rvmyth/ cd rvmyth iverilog mythcore_test.v tb_mythcore_test.v ./a.out gtkwave tb_mythcore_test.vcd
Design a PLL as a clock multiplier using verilog and test the functionality.
iverilog avsd_pll_1v8.v pll_tb.v
./a.out
gtkwave test.vcd
Now integrate both rvmyth and avsdpll using a top level testbench and test it to verify.
iverilog rvmyth_pll.v rvmyth_pll_tb.v
./a.out
gtkwave test1.vcd
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault,SPEF-Extractor and custom methodology scripts for design exploration and optimization (https://github.com/efabless/openlane).
The OpenLANE and sky130 installation can be done by referring this repository https://github.com/nickson-jose/openlane_build_script.
Once installation is done the next step is synthesis.
In OpenLANE the RTL synthesis, technology mapping and timing reports are performed by different tools.
- RTL synthesis by yosys.
- Technology mapping by abc.
- Timing reports are generated by OpenSTA.
Verilog file (.v) of the avsdpll and its LIB (.lib) file.
To generate the LIB file run the below perl script.
perl verilog_to_lib.pl avsdpll.v avsdpll
To perform synthesys in yosys
- Just type yosys in linux shell and follow the script.
read_verilog rvmyth_pll.v
read_liberty -lib avsd_pll_1v8.lib
read_liberty -lib sky130_fd_sc_hd__tt_025C_1v80.lib
synth -top rvmyth_pll_interface
dfflibmap -liberty sky130_fd_sc_hd__tt_025C_1v80.lib
opt
abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib -script +strash;scorr;ifraig;retime;{D};strash;dch,-f;map,-M,1,{D}
flatten
setundef -zero
clean -purge
rename -enumerate
stat
write_verilog -noattr rvmyth_pll.synth.v
The synthesized netlist is rvmyth_pll.synth.v
The snapshot of the synthesized netlist.
Now, with the generated netist simulate it in iverilog and check the results in gtkwave to compare the pre-synth and post-synth simulations. To achieve that first a GLS testbench file should be written in verilog to compare the results. The pre-synth and post-synth simulation output must be same.
Use the following commands for pre-synth simulation output.
iverilog rvmyth_pll.v rvmyth_pll_tb.v
./a.out
gtkwave test1.vcd
Use the following commands for post-synth simulation output.
iverilog gls.v
./a.out
gtkwave gls.vcd
- https://github.com/vsdip/avsdpll_1v8_sky130_ss
- https://github.com/vsdip/vsdmixedsignalflow
- https://github.com/nickson-jose/vsdstdcelldesign
- https://gitlab.com/gab13c/openlane-workshop
Mr.Kunal Ghosh Co-founder of VLSI System Design Pvt. Ltd.
Shivani Shah, IIIT Bangalore.
Mili Anand, M.Tech VLSI Design, Indira Gandhi Delhi Technical University for Women (IGDTUW).