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Merge branch 'fix-tests'
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MaZderMind committed Feb 11, 2018
2 parents 21a9b2b + 23fc23c commit 5659fef
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Showing 4 changed files with 26 additions and 18 deletions.
6 changes: 4 additions & 2 deletions voctocore/lib/pipeline.py
Original file line number Diff line number Diff line change
Expand Up @@ -119,5 +119,7 @@ def __init__(self):

if Config.has_option('mix', 'slides_source_name'):
port = 15001
self.log.info('Creating SlideStreamBlanker-Output at tcp-port %u', port)
self.slides_streamout = AVRawOutput('slides_stream-blanker_out', port)
self.log.info(
'Creating SlideStreamBlanker-Output at tcp-port %u', port)
self.slides_streamout = AVRawOutput(
'slides_stream-blanker_out', port)
10 changes: 10 additions & 0 deletions voctocore/tests/helper/voctomix_test.py
Original file line number Diff line number Diff line change
Expand Up @@ -20,3 +20,13 @@ class VoctomixTest(unittest.TestCase):

def setUp(self):
lib.config.Config.resetToDefaults()

def assertContainsIgnoringWhitespace(self, text, search):
regex = search.replace(" ", "\s*")

try:
self.assertRegex(text, regex)
except AssertionError:
raise AssertionError("search-string was out found in text (ignoring whitespace)\n"
"search-string %s\n"
"text:\n%s" % (search, text))
Original file line number Diff line number Diff line change
Expand Up @@ -17,25 +17,27 @@ def setUp(self):

def test_unconfigured_does_not_add_a_deinterlacer(self):
pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(pipeline, "videoconvert ! videoscale")
self.assertContainsIgnoringWhitespace(pipeline, "videoconvert ! videoscale")

def test_no_does_not_add_a_deinterlacer(self):
Config.given("source.cam1", "deinterlace", "no")

pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(pipeline, "videoconvert ! videoscale")
self.assertContainsIgnoringWhitespace(pipeline, "videoconvert ! videoscale")

def test_yes_does_add_yadif(self):
Config.given("source.cam1", "deinterlace", "yes")

pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(pipeline, "mode=1080i50 ! yadif mode=interlaced ! videoconvert")
self.assertContainsIgnoringWhitespace(
pipeline,
"mode=1080i50 ! videoconvert ! yadif mode=interlaced ! videoconvert")

def test_assume_progressive_does_add_capssetter(self):
Config.given("source.cam1", "deinterlace", "assume-progressive")

pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(
self.assertContainsIgnoringWhitespace(
pipeline,
"mode=1080i50 ! capssetter caps=video/x-raw,interlace-mode=progressive ! videoconvert"
)
Expand All @@ -49,7 +51,3 @@ def simulate_connection_and_aquire_pipeline_description(self):
pipeline = args[0]

return pipeline

def assertRegexAnyWhitespace(self, text, regex):
regex = regex.replace(" ", "\s*")
self.assertRegex(text, regex)
Original file line number Diff line number Diff line change
Expand Up @@ -20,25 +20,27 @@ def setUp(self):

def test_unconfigured_does_not_add_a_deinterlacer(self):
pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(pipeline, "demux. ! video/x-raw ! queue ! tee name=vtee")
self.assertContainsIgnoringWhitespace(pipeline, "demux. ! video/x-raw ! queue ! tee name=vtee")

def test_no_does_not_add_a_deinterlacer(self):
Config.given("source.cam1", "deinterlace", "no")

pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(pipeline, "demux. ! video/x-raw ! queue ! tee name=vtee")
self.assertContainsIgnoringWhitespace(pipeline, "demux. ! video/x-raw ! queue ! tee name=vtee")

def test_yes_does_add_yadif(self):
Config.given("source.cam1", "deinterlace", "yes")

pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(pipeline, "demux. ! video/x-raw ! yadif mode=interlaced name=deinter")
self.assertContainsIgnoringWhitespace(
pipeline,
"demux. ! video/x-raw ! videoconvert ! yadif mode=interlaced name=deinter")

def test_assume_progressive_does_add_capssetter(self):
Config.given("source.cam1", "deinterlace", "assume-progressive")

pipeline = self.simulate_connection_and_aquire_pipeline_description()
self.assertRegexAnyWhitespace(
self.assertContainsIgnoringWhitespace(
pipeline,
"demux. ! video/x-raw ! capssetter caps=video/x-raw,interlace-mode=progressive name=deinter"
)
Expand All @@ -52,7 +54,3 @@ def simulate_connection_and_aquire_pipeline_description(self):
pipeline = args[0]

return pipeline

def assertRegexAnyWhitespace(self, text, regex):
regex = regex.replace(" ", "\s*")
self.assertRegex(text, regex)

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