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Viktor Nikolov edited this page Oct 10, 2023 · 68 revisions

Other pictures are available here.

List of the carrier board features

  • 106 digital I/O pins exposed via female headers

    • 16 I/O pins work on 5 V (exposed via two PMOD headers), and the rest of the pins work on 3.3 V

  • 2 dedicated analog input pins XADC VP/VN

  • 2 LEDs

  • 2 push buttons

  • 50 MHz precision oscillator (intended as an external clock input to the FPGA Programmable Logic)

  • UART to USB conversion chip with the micro-USB connector (intended to enable UART communication for the FPGA Programmable Logic)

  • Power input via micro-USB connector or screw terminal. On board power switch.

  • Compatible with both MicroZed 7010 and MicroZed 7020.

How to use

Powering the board

The default way to power the board is micro-USB connector CON1, which has no other function but a 5 V power supply. Connecting power to CON1 (or terminal J1) is mandatory for the MicroZed + the board to operate.

When also the micro-USB connector on the MicroZed is connected to a computer, the two micro-USB connectors contribute to the current delivery for both MicroZed and the board.

I put a power switch on the board. When the board is connected to the power and the switch is off, the PWR_ENABLE signal of MicroZed is driven low, and the MicroZed is shut down.

Green LEDs marked "LED 5V" and "LED 3.3V" indicate that the respective power rails are powered up.

Alternatively, the board can be powered from a lab power supply via screw terminal J1. J1 is meant to be soldered DIY; production files don't contain it.

⚠️WARNING

There is no polarity protection on the terminal J1. I didn't want a voltage drop of a protective diode.

In the case of wrong polarity, components on the carrier board will be damaged, but the MicroZed will be safe. The MicroZed has a protective Schottky diode D9 on its 5 V input.

Pinout

Digital I/O pins

Digital I/O pins are available on two big female headers J3 and J4, and three PMOD headers. Both vertical and horizontal PMOD headers can be soldered on the board. All headers are meant to be soldered DIY; production files don't contain them.

Please refer to this folder to "MicroZed carrier JX pinout table" (PDF, XLS). The table lists all signals coming from the MicroZed via mezzanine connectors JX1 and JX2 and their mapping to pins on the board. The table also includes information about the impedance of a trace (or differential pair) connecting a given JX1/JX2 pin to the header (where applicable).

The master .xdc file of constraints for Vivado is provided, which is sorted and grouped according to the numbering of pins on the board.

⚠️WARNING

Digital I/O connected to PMOD1 and PMOD2 is shifted to 5 V level and accepts 5 V input.

TI TXB0108 voltage-level shifter is used with a rated throughput of 100 Mbps.

All other digital I/O (PMOD3, J3, J4) is 3.3 V (and is not 5 V tolerant).

Analog input

ZYNQ dedicated analog input differential pair XADC VP/VN is connected to pins J3_46/J3_47.

Please note that some auxiliary analog inputs _ADxP_ and _ADxN_ are not usable as analog inputs because I used them as digital I/O pins for LED1, SWITCH1, PMOD1 and PMOD2 (there is a voltage level shifter between PMOD1/2 and ZYNQ). Consult the JX2 pinout table in the folder constraints_and_pin_description for details.

LEDs and switches

Four MicroZed digital pins are connected to two tactile switches and two yellow LEDs. See MicroZed_carrier_board_constraints_master.xdc for the definition of ports.

50 MHz oscillator

Precise 50 MHz oscillator is connected to ZYNQ pin N18 (IO_L13P_T2_MRCC_34).

The motivation for having this oscillator is to test external clock input into the FPGA Programmable Logic.

The oscillator can also be used as a clock input for the FPGA Programmable Logic testing without the Zynq Processing System running. The Zynq PS clock signal FCLK_CLK0 outputs the 100 MHz clock only when an application runs on the PS ARM cores. On the other hand, the carrier board's 50 MHz oscillator runs always.

Nevertheless, the oscillator can be removed from the production files to save cost.

This screenshot from a scope shows the oscillator signal (measured with MicroZed attached):

UART to USB

In my project, I'm often using UART to output debug data directly from the Programmable Logic using AXI UART Lite IP. To make it easier, I put a USB to serial conversion chip on the board accessible via the UART Micro-USB connector (this connector doesn't provide any power to the board, just a USB connection).

UART to USB how-to:

  • TX signal of the AXI UART Lite IP needs to be connected to the ZYNQ pin U20 (named J3_33_UART_TX in the master .xdc file). RX signal should go to ZYNQ pin T20 (named J3_32_UART_RX in the master .xdc file).
  • Connect your computer to the board's UART Micro-USB connector. A new COM port should become available in the operating system. Connect a terminal program (e.g. PuTTY) to a given COM port, and set the COM port speed to match the speed configured on the AXI UART Lite IP.
  • My experience is that on Windows and Ubuntu no driver installation is needed. If you face a missing driver problem, download the CH340 IC driver from the CH340 IC manufacturer.
    • ⚠️ WARNING: On Ubuntu 22.04.1 (and other versions) a braille display driver is in conflict with CH340 USB serial (see discussion here). The issue is resolved by uninstalling BRLTTY by the command sudo apt remove brltty.
  • The activity of the board's serial output/input is indicated by yellow TX LED and green RX LED on the board.
  • I wrote a simple Verilog module write_to_uart which connects to AXI UART Lite IP via AXI and exposes a simple interface for "printing" strings up to 16 characters long. See the board demo project for an example of use.

Power and ground headers

Female headers J5 and J7 are available for powering components connected to the board with 5 V and 3.3 V.

The 5 V to 3.3 V regulator TPS62082 used on the board is rated for a maximum current of 1.2 A (I successfully tested it up to 1.2 A).

Headers J2 and J7 provide ground. I soldered male headers on J2 and J7 and am using them to connect ground leads of scope probes.

Test points

Several test points are on the board with the tested signal name marked on the silkscreen.

VIN, VCCIO and 50 MHz oscillator test points are intended to be used by a scope probe with short wire ground lead.

Test jumpers

JP1 (3.3 V rail testing):

  • Normally, the 3.3 V power rail is activated only when MicroZed is attached to the board and powered up. The signal VCCIO_EN from the MicroZed enables the 5 V to 3.3 V regulator on the board during the MicroZed power-up sequence.

  • To test the 3.3 V power rail without MicroZed attached, the jumper JP1 can be shorted. This enables the output of the 5 V to 3.3 V regulator.

JP2 (PUDC):

  • JP2 configures pull-up during config (PUDC). See Configuration Pin Definitions in the UG470 for details.
  • When JP2 pins 1 and 2 are shorted, or no pins of JP2 are shorted (default setting), PUDC_B is driven high, and internal pull-up resistors are disabled on each SelectIO pin during the ZYNQ configuration. Therefore, the SelectIO pins will be floating.
  • When JP2 pins 2 and 3 are shorted, PUDC_B is driven low, and internal pull-up resistors are enabled on each SelectIO pin during the ZYNQ configuration.
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