Skip to content

Digital Circuits Lab (2017 Spring) @ National Taiwan University

Notifications You must be signed in to change notification settings

victoresque/DCLab

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

12 Commits
 
 
 
 
 
 
 
 

Repository files navigation

DCLab

Digital Circuits Lab (2017 Spring)

Requirements

  • Quartus 16
  • DE2-115 FPGA board

Digital Circuits Lab

Lab 1

Pseudo-random number generator on FPGA

Lab2

RSA decoder on FPGA, using Python for serial data trasmission on RS-232 interface

Lab3

Audio recorder on FPGA using SDRAM, more details in report (Chinese)

Final Project

A NIOS-II system that can load 3D models from SD card and render them on the screen in real time, link: https://github.com/victoresque/FPGA-Renderer


數位電路實驗

實驗一

在 DE2-115 上實作亂數產生器

實驗二

實作 RSA 解碼器,利用 RS-232 介面和 Python 進行資料傳輸

實驗三

實作簡單的錄音機,細節請參考 Report

期末專題

基於 NIOS-II 的實時 3D 渲染。 https://github.com/victoresque/FPGA-Renderer

About

Digital Circuits Lab (2017 Spring) @ National Taiwan University

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published