This repository contains a tool for converting asynchronous circuits into equivalent synchronous models.
The models can be used as drop-in replacements for async circuits in conventional (sync) simulation and formal verification, enabling users to leverage existing (sync) tools, design flows, formalisms and knowledge to simulate and verify async circuits.
Generated circuits have the same interface as input circuits but with added
clk and reset pins.
For more information on the tool please refer to:
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The paper Formal Verification of Mixed Synchronous Asynchronous Systems using Industrial Tools
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The accompanying presentation slides