Pinned Loading

1. Asynchronous_FIFO Asynchronous_FIFO Public

   Design an asynchronous FIFO to safely pass data from one clock domain to another asynchronous clock domain

   1

2. Round_Robin_Arbiter Round_Robin_Arbiter Public

   Design a round-robin arbiter to ensure that each request has an equal chance of being granted access to shared resources.

   SystemVerilog 1

3. Pipeline_Optimized_Carry_Look_Ahead_Adder Pipeline_Optimized_Carry_Look_Ahead_Adder Public

   Design a pipeline and high-performance carry-look-ahead adder and verify using automated comparison testbench

   Verilog 1

4. Nbit_Bidirectional_Shift_Register Nbit_Bidirectional_Shift_Register Public

   Desig a bidirectional shift register with parameterized width

   Verilog 1

5. Parking_System_Moore_Machine Parking_System_Moore_Machine Public

   Design a parking system that can verify the password and control the gate when the entrance and exit sensors detect an approaching vehicle

   Verilog 1

6. Traffic_Light_Controller_Mealy_Machine Traffic_Light_Controller_Mealy_Machine Public

   Designing a traffic light controller to coordinate traffic lights on highways and farm ways

   Verilog 1