Enable vclk after video engine initialization
to fix memory corruption issue after cold boot

Change-Id: I4f972b0f2601958ea4d5557b8569f76452eed2ef

add to support multi-master mode for i2c bus 4 and 13
for MCTP over smbus data transmission.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Change-Id: If68eb5f18dd4f4c2a37d8d58b77f3f55141419c8

This reverts commit b3fa0ba.

Change-Id: I30408b743cc2388e4252f7a660c2dfcaa5a42c1c

Use the driver, drivers/media/platform/aspeed-video.c, instead.

Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com>
Change-Id: Ie12daf99c4ebda186cdb52694c202584230c3d8d

Add TPM related configurations on AST2600 platform.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ia681683aa1327f9b75b408933c896562369ca2b6

enable vclk after eclk for Video Engine

Change-Id: I4c0eb677dd32908527b2a657d1bf52eb05263c5f

This patch add the HDR function for master to send the ccc or data with
HDR mode to the device.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I98b5b4088d663b4f846e5079cee90eabe25e3afe

This patch implements the HDR transfer function for aspeed i3c master.
Currently, the master only support the HDR-DDR mode.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I8edd56a4b35c24e2e0fe182516f5c211d4f445de

This patch will use HDR-DDR mode to send the i3c data if the device
support it and the CONFIG_I3CDEV_XFER_HDR_DDR say 'y'.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I682405cb460c33fdbcc81962af4076beceebe29c

Add the condition to separate the ibi and response ready interrupt.
Before this patch the master will signal the completion of the thread,
either ibi or response ready interrupt. However, the completion should
only wait for response ready interrupts instead of the ibi. The
unexpected wake-up by ibi will result in the process stuck or kernel panic

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I8c27f83dee1779394e131577b2920ea6a508a79a

The user may send the endstate with JTAG_STATE_CURRENT, the driver
should replace it with the state store in the drvier.

Reported-by: Jim Heck <jim.heck@oracle.com>
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I1afa4cdccd98ecd2e9a8be45f85657247c3cb4de

The default value of the control register is set using the direct
mapping information passed to the ->dirmap_create() handler. Dump the
mapping range and the SPI memory operation characteristics to analyze
how the register value has been computed.

spi-aspeed-smc 1e630000.spi: CE0 read dirmap [0x00000000 - 0x04000000]
OP 0x6c mode:1.1.1.4 naddr:0x4 ndummies:0x1
...
spi-aspeed-smc 1e630000.spi: CE0 write dirmap [0x00000000 - 0x04000000]
OP 0x12 mode:1.1.0.1 naddr:0x4 ndummies:0x0

Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220622161617.3719096-2-clg@kaod.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ia62588a21fa4933b9a17a8740cd85b845ded018e

When using the normal read operation for data transfers, the dummy bus
width is zero. In that case, they are no dummy bytes to transfer and
setting the dummy field in the controller register becomes useless.

Issue was found on a custom "Bifrost" board based on the AST2500 SoC
and using a MX25L51245GMI-08G SPI Flash.

Reported-by: Ian Woloschin <ian.woloschin@akamai.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Tested-by: Ian Woloschin <iwolosch@akamai.com>
Fixes: 9da06d7 ("spi: aspeed: Add support for direct mapping")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220622161617.3719096-3-clg@kaod.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I63c492693e76facad7ef31995587a3606382d1f7
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>

Both quad SPI TX and RX modes can be supported on AST2600.
Correct typo in mode_bits field in both ast2600_fmc_data
and ast2600_spi_data structs.

OpenBMC-Staging-Count: 1
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20221005083209.222272-1-chin-ting_kuo@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Change-Id: I0c13cc518e71c86a2f1fbab114cf6ab869714234

The offset value of the mapping window in the kernel structure is
calculated using the value of the previous window offset. This doesn't
reflect how the HW is configured and can lead to erroneous setting of
the second flash device (CE1).

OpenBMC-Staging-Count: 1
Fixes: e3228ed ("spi: spi-mem: Convert Aspeed SMC driver to spi-mem")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20221016155722.3520802-1-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
Change-Id: I44bc77de5cfdcb036372bcdda6c9467fea76cee9
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>

For some flash parts, the original delay timing may
be in the margin point. Thus, we extend the delay timing
in order to satisfy the reset sequence for the most
flash parts.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I7cf2175a604a1aa5bb4071fb0c9a4f4c0ed4ca0a

The "chunk >= 0" condition does not work because count is a u32.
Also, really we shouldn't enter the loop when "chunk" is zero.

Once that condition is fixed then there is no need for the "last"
variable.  I reversed the "if (chunk <= ep->chunk_max)" as well.
The new loop is much simpler.

Fixes: 055276c ("usb: gadget: add Aspeed ast2600 udc driver")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Change-Id: Ia074b01d1fde7ae3936ef8030bcb521ac432ce7d

The bug is that we should still enter this loop if "tx_len" is zero.

After adding the "last" variable, then the "chunk >= 0" condition is no
longer required but I left it for readability.

Reported-by: Neal Liu <neal_liu@aspeedtech.com>
Fixes: c09b1f3 ("usb: gadget: aspeed_udc: cleanup loop in ast_dma_descriptor_setup()")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Neal Liu <neal_liu@aspeedtech.com>
Change-Id: I7d169525424de001c6337ac77a16e51d03fbb7ad

Add operation configuration for CRTM enabled scenario.
- Use command mode to access flash.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I1ce8db4224d047f4e1f7e3a6fa5855916a743698

Problem:
    CDC NCM low performance issue. BULK IN transfer error - illegal
NDP (NCM Datagram Pointers) Signature.

Solution:
    The udc descriptor(DMA) mode allowable transfer length is 4096 bytes.
Wrong tx_len will result in decoding NDP16 field error, the iperf testing
results would be abnormal. Correct it to fix CDC NCM performance drop
issue.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Change-Id: Iae60890cd96ec1e338c2e23ae5a228e42ec278cd

The node names of spd has changed by the patch:
commit ee4117e ("ARM: dts: ast2600-evb: use macro to creat I3C SPD
child node")

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I97d66570aea3b4ec5e48c63d83e05e650dfb40fa

afm-act will be inside ast1060, and the afm-stg will be used as staging
area for image update.

afm-rcv is the recovery area for recovering.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Change-Id: I4cd52ebdd69dd4fef51a66ec0dde6e8b9694fdf3

- Using the expected SPI clock frequency when user mode is used.
- Using the SPI clock frequency in device tree if the better
  clock frequency is not found.

Change-Id: I72490a825d6ec7353565e32571ba8cd939092503
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>

Clear the rx_warmup flag when any valid packet is found to avoid
unexpected runaway rx packet modifying the MCTP's boundary of rx buffer.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I69dd1e55ff39548f816024e1926a519c980bde4e

The rx length shouldn't bigger than the MTU size. This patch add the
warning log to alarm this problem for debugging.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I687df11ecd0e2025c0f9caa69c0375fe4257c715

Transfer error interrupt will generate one response data, so append this
condition to handle the response data for the xfer error.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I234c846f462e0f4d3c31c4308e8090c674bfe679

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I9c55844d9b2fbf1cad07c2a8f1a514ca6e4f561d

Rx runaway will only occur when rx warmup and packets may not have been
written to the dram when the driver enter the rx tasklet by the interrupt.
If the packet write to the dram after check the packet in sw_ptr, the rx
runaway will be detected by mistake and cause the packet sequence to go
wrong. So this patch add the condition to avoid the driver to check the
runaway packet after getting first valid packet.

Failed log:
[  512.642350] aspeed-mctp 1e6e8000.mctp: Runaway RX packet found 79 -> 80 (b204f900)
[  512.650895] aspeed-mctp 1e6e8000.mctp: Hw read ptr = 004f004f
[  512.657339] aspeed-mctp 1e6e8000.mctp: Hw read ptr = 00510051
[  512.663851] aspeed-mctp 1e6e8000.mctp: Address 84953160
[  512.669706] aspeed-mctp 1e6e8000.mctp: VDM header:
[  512.675135] aspeed-mctp 1e6e8000.mctp: 72 00 00 10
[  512.680549] aspeed-mctp 1e6e8000.mctp: 40 00 30 7f
[  512.685918] aspeed-mctp 1e6e8000.mctp: 01 00 1a b4
[  512.691315] aspeed-mctp 1e6e8000.mctp: 01 0b 09 70 ==> SOM = 0, EOM = 1, seq = 3
...
[  512.788905] aspeed-mctp 1e6e8000.mctp: Runaway RX packet found 82 -> 79 (b204f8b0)
[  512.797518] aspeed-mctp 1e6e8000.mctp: Hw read ptr = 00520052
[  512.804060] aspeed-mctp 1e6e8000.mctp: Hw read ptr = 00520052
[  512.810548] aspeed-mctp 1e6e8000.mctp: Address 84953c60
[  512.816418] aspeed-mctp 1e6e8000.mctp: VDM header:
[  512.821838] aspeed-mctp 1e6e8000.mctp: 72 00 00 10
[  512.827252] aspeed-mctp 1e6e8000.mctp: 40 00 00 7f
[  512.832688] aspeed-mctp 1e6e8000.mctp: 01 00 1a b4
[  512.838075] aspeed-mctp 1e6e8000.mctp: 01 0b 09 20 ==> SOM = 0, EOM = 0, seq = 2
...
[  513.291771] aspeed-mctp 1e6e8000.mctp: Runaway RX packet found 80 -> 82 (b204f9a0)
[  513.300358] aspeed-mctp 1e6e8000.mctp: Hw read ptr = 00530053
[  513.306819] aspeed-mctp 1e6e8000.mctp: Hw read ptr = 00530053
[  513.313341] aspeed-mctp 1e6e8000.mctp: Address 84953420
[  513.319221] aspeed-mctp 1e6e8000.mctp: VDM header:
[  513.324654] aspeed-mctp 1e6e8000.mctp: 72 00 00 03
[  513.330066] aspeed-mctp 1e6e8000.mctp: 16 00 20 7f
[  513.335458] aspeed-mctp 1e6e8000.mctp: 01 00 1a b4
[  513.340883] aspeed-mctp 1e6e8000.mctp: 01 0b 0a c0
...

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Ie1efad49b2847e172794e0194c8319c1448c728c

Schedule the rx tacklet when user try to poll/read the packets to avoid
the rx tasklet triggered by interrupt not finding a valid packet to
improve the performance.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Ie2fa4938bf716b5dfd9c60e770d9f3ae590b226e

Add the support for the ast10x0 a2 device.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I58718b135e69d89fedc8c099e73873bc641cac7f

Force i2c irq status into i2c irq handle if the i2c error is occurred.

Signed-off-by: Tommy Huang <tommy_huang@aspeedtech.com>
Change-Id: I9ae427b8c53519147a02ca920254fff27de65929

Signed-off-by: ryan_chen <ryan_chen@aspeedtech.com>
Change-Id: I5e75ebac1cc68ce18debb1fed7d1c3c168f8bb72

The dummy read can ensure the register write has been completed to avoid
bus delays affecting the real TCK frequecy.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Ibc1f12b624b450052c91ce6151ebaa6b60a46ef5

To meet the frequency setting in user space, the ndely during TCK
transition should be the half of sw_delay.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I4f2e7ea868e4873468eef4e1203a1b9240a29d0d

Signed-off-by: ryan_chen <ryan_chen@aspeedtech.com>
Change-Id: I62f6b6a00a27ae4d25e59e00dfe092a38b6d5841

do the same check as commit 8654464 ("i3c: master: dw: check return
of dw_i3c_master_get_free_pos()")

"pos can be negative because dw_i3c_master_get_free_pos() can return an
error.  So check for an error."

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I396c326781404b6285b29200d2373ed156bb92ae

JESD403 specifies it doesn't support hot-join so just don't enable it in
the driver probe.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I6762d1ebc4e56ee17c2f6692994de43681d850f8

There are 3 bits to represent key numbers, change mask
from 0x3 to 0x7.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Change-Id: If33ad0fd1ae4bbd56357b12c97bce6b9f602a584

Update the PCIE regmap name from ast2600-pcie-ep into ast2600-pcie-phy

Signed-off-by: Tommy Huang <tommy_huang@aspeedtech.com>
Change-Id: I94fbc4d7dc41d4cfb91d4d3ee5e1b50ddd06782a

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Change-Id: Ia9fa7bc6782a14ecf149962e9bb989590e4b2fb0

Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code.
No functional change.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com>
Change-Id: I3a1c86c93caafe0af8408b308f5ca6ea736870ac

Add cpld staging region for PFR 4.0 CPLD Update feature.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ieff35086990fbbe2d37076162270b42c5864f317

Disable hold/reset pin function on MT25QL02G flash part.
If QSPI mode is used and the IO rising time is not good,
the flash will be in hold/reset status when the next QSPI
command is sent.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Idfbb25f39e4d99205c981b7fd8ba749fb2c3ea7a

pcei -> pcie.
The usage of the property should be:
&pciecfg {
        pcie1-perst-gpios = <&gpio0 ASPEED_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
        ...
};

Fixes: 99a05d6 ("pcie: Handle PERST signal from the gpio.")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: If064c272ad834e8b68187d8cacdad4d74a1973d6

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Change-Id: I921182a5044cb4c75d564d9f18572b8cbbb7237f

…ehavior

The I3C3/4 controllers have the capability to configure the function to
operate at either high or low voltage pins depending on specific
scenarios. However, simultaneous activation of both voltage pins should
be avoided to prevent undesired behaviors in the I3C.
This patch introduces a dependency for the register setting to ensure that
such a situation is avoided.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I509f2b6ea1b966ad696134cd68a937d39e49fd37

SCU474 is a non-existent register, so remove the code that accesses it.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9abd3b5724f821e513c06fec9b5437c3e94d5b75

reset the queues and resume the controller if it goes into the halt state.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I6af6ea66013baf17fcb711a238f5acfb448d8baa

MIPI I3C v1.1 indicates "for devices with BCR bit 2 set to 1'b1, the Max
IBI payload size value is added as a third byte". So the payload length
of the SETMRL CCC is
2, if BCR[2] is 1b0
3, if BCR[2] is 1b1

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I6f964f8a6dcdeb1c9819c51bd0baf11c13374992

Use FIELD_PREP/FIELD_GET to set/get the bit fields of the device address
table (DAT).

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I290e9209808c62fa5e0f5bedd3fff7a16543243a

1. save parity bit value in the software DAT
2. do not enable IBI address mask by default
3. keep SIR_REJECT and MR_REJECT be 1 even if the DAT is not used

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I1b68077f0894d0139adb733e1af5bcdd18079827

The interrupt resp_q_ready indicate the event of ibi transfer done, data
read by master and master write data. The differnet of these events list
below:
1. if it include the signal ibi_update: ibi transfer done
2. if the response data contain the data length > 0: master write data.
3. others: data read by master.
This patch separates the wait event of the ibi and data consume by TID
and interrupt status, making ISR can signal the appropriate event.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I90e4663b4aa2e6db0400f06829bedc670c26c331

Add 1.8V w25q512nw flash part in the flash ID list.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: If41c68333d4e73e3b61c002a79ad64d0f8d78786

Fix typo.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Change-Id: I3de6edfec0b234ddbafa91c419b5184e2b3daa37

The function i3cdev_send_hdr_xfer() can allocate data_ptrs[i] with
length xfers[i].len, however the allocation size must be rounded up to
the nearest 2-byte boundary, as the hdr transfer are 16-bit aligned.
This patch fixes this issue by allocating the data_ptrs[i] with the
roundup size to avoid the extra byte sent isn't initialized.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Ib099caf80ed6b2b0939187e73f7b16647d94cabe

Before the reset FIFO,the i3c controller should be disabled to avoid the
incomplete resetting. After that the i3c controller should be enabled to
avoid the next transfer to fail.
The enable bit of the i3c slave mode require the scl to active, but we
can't control the scl in slave mode. So, this patch add the api to use
the software force mode to generate the dummy scl_in signal which won't
affect external signal to active the bit.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Idebd9ae2745927ab2db294a5ff7554685857a8a2

Our i3c controller is based on the MIPI i3c v1.0, but the target reset
pattern was introduced in MIPI i3c v1.1.1. So, we need to use the software
mode to generate the pattern to be compatiable with the future's i3c
devices.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I611c74e1b1a8901439a0ecb741ceec96b24c39ec

Under certain conditions, such as when an IBI interrupt is received and
SDA remains high after the address phase, the i3c master may enter an
infinite loop while trying to read data until the t-bit low appears.
This commit addresses the issue by gerenating the fake t-bit low to stop
the IBI storm when receiving an IBI with an unrecognized address or when
the received data length of IBI is larger than the maximum IBI payload.
This issue can't be solved by abort function, because it doesn't work when
i3c fsm at Servicing IBI Transfer (0xe) and Clock extension state (0x12).

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I987c917330d0f9650fe00b24fede3d2670cfc1ea

…y occurred.

When an IBI is received with the PEC error flag set, the patch checks if
the received message matches one of the entries in a pre-defined MDB
table. This is because when an IBI with a repeat start and get CCC is
received, the PEC error flag will also be set.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I93693ef92cf133b00a6def1a2d39307521b36f0b

To handle the PEC issue in a flexible manner, the procedure should be
postponed to the device driver instead of creating predefined mdb table
within the i3c driver.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I6f9fcb612726c90ce353e0fa96040547c60065c1

When an IBI status is received with the PEC error flag set, further
matching with the mdb table to ensure the pec error actually occurred.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I1052fe864480e1f58389015c4b414a773f56f82a

The software DAT (group DAT) is designed for JESD403. In general MIPI
context, use different DAT for different dynamic address as possible.
This can prevent the swapping of the HW DAT setting during operation
time.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9883db5223b5994392ce48f6a36fe85d9bc0a50f

Cisco reported a TX queue timeout issue which can only be reproduced on
their platform. They have created this patch for it and verified its
effectiveness on their platform. Aspeed also confirmed that there are no
adverse effects from the patch.

The log is as below:

```
[ 1649.992710] ------------[ cut here ]------------
[ 1649.992740] WARNING: CPU: 1 PID: 3982 at net/sched/sch_generic.c:478 dev_watchdog+0x2e4/0x2e8
[ 1649.992777] NETDEV WATCHDOG: eth0 (ftgmac100): transmit queue 0 timed out
[ 1649.992786] Modules linked in: ast2600_i3c_master rvas_video g_mass_storage usb_f_mass_storage g_ether usb_f_ecm usb_f_rndis u_ether usb_f_hid g_hid tpm_tis_spi tpm_tis_core ast2600_i3c_global peci_driver block_transfer_driver aspeed_mctp pmbus_driver watchdog_driver [last unloaded: ast2600_i3c_master]
[ 1649.992884] CPU: 1 PID: 3982 Comm: rfc_main_daemon Not tainted 5.15.48.3 #2
[ 1649.992897] Hardware name: Generic DT based system
[ 1649.992905] Backtrace:
[ 1649.992914] [<80b33d08>] (dump_backtrace) from [<80b33f4c>] (show_stack+0x20/0x24)
[ 1649.992938]  r7:000001de r6:00000009 r5:80d68218 r4:60070113
[ 1649.992944] [<80b33f2c>] (show_stack) from [<80b393d4>] (dump_stack_lvl+0x48/0x54)
[ 1649.992962] [<80b3938c>] (dump_stack_lvl) from [<80b393f8>] (dump_stack+0x18/0x1c)
[ 1649.992981]  r5:80980b94 r4:80e11488
[ 1649.992986] [<80b393e0>] (dump_stack) from [<80121d04>] (__warn+0xfc/0x114)
[ 1649.993005] [<80121c08>] (__warn) from [<80b345cc>] (warn_slowpath_fmt+0xa8/0xdc)
[ 1649.993024]  r7:000001de r6:80e11488 r5:80e1144c r4:891e8000
[ 1649.993030] [<80b34528>] (warn_slowpath_fmt) from [<80980b94>] (dev_watchdog+0x2e4/0x2e8)
[ 1649.993052]  r9:00000001 r8:81d03d00 r7:843a5000 r6:823d5600 r5:843a5264 r4:00000000
[ 1649.993058] [<809808b0>] (dev_watchdog) from [<801a34b0>] (call_timer_fn+0x40/0x198)
[ 1649.993083]  r9:b3e9a5c0 r8:00020f58 r7:809808b0 r6:00000100 r5:843a5264 r4:843a5264
[ 1649.993089] [<801a3470>] (call_timer_fn) from [<801a4850>] (run_timer_softirq+0x588/0x640)
[ 1649.993109]  r8:00000000 r7:891e9e94 r6:00020f58 r5:00000000 r4:843a5264
[ 1649.993114] [<801a42c8>] (run_timer_softirq) from [<8010146c>] (__do_softirq+0x154/0x3bc)
[ 1649.993137]  r10:ffffe000 r9:7e9889e0 r8:00000202 r7:00000100 r6:00000001 r5:00000002
[ 1649.993144]  r4:81d03084
[ 1649.993149] [<80101318>] (__do_softirq) from [<801298e4>] (irq_exit+0xc4/0x108)
[ 1649.993171]  r10:ffffffec r9:7e9889e0 r8:81cd2fdc r7:0000001d r6:00000000 r5:00000000
[ 1649.993177]  r4:ffffe000
[ 1649.993182] [<80129820>] (irq_exit) from [<8017ec78>] (handle_domain_irq+0x70/0x88)
[ 1649.993200]  r5:00000000 r4:81cd2fd0
[ 1649.993206] [<8017ec08>] (handle_domain_irq) from [<80101294>] (gic_handle_irq+0x7c/0x90)
[ 1649.993226]  r7:891e9fb0 r6:b780200c r5:b7802000 r4:81d06a64
[ 1649.993231] [<80101218>] (gic_handle_irq) from [<80100eb4>] (__irq_usr+0x54/0x80)
[ 1649.993247] Exception stack(0x891e9fb0 to 0x891e9ff8)
[ 1649.993259] 9fa0:                                     7480f938 7480f93c 7480f938 00000004
[ 1649.993270] 9fc0: fefefeff 7480f938 76c8ca8c 00000152 7e9889de 7e9889e0 ffffffec 769e5964
[ 1649.993280] 9fe0: 76c8cb60 769e57d0 80808080 76adaa80 20070010 ffffffff
[ 1649.993292]  r9:7e9889e0 r8:10c5387d r7:10c5387d r6:ffffffff r5:20070010 r4:76adaa80
[ 1649.993313] ---[ end trace 10866acd29252664 ]---
```

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: If1a78b3389b35a0a2b9ae111f6c3d5b3631446a2

To provide more demonstrations of I3C usage, revise the I3C target
devices in the device tree. I3C0 to I3C3 connect to the Aspeed I3C
daughter board, where I3C0 and I3C1 operate in I3C mode, while I3C2 and
I3C3 operate in I2C mode. I3C4 and I3C5 are tied together to provide a
loopback demonstration.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9bdc6358f90dd4121f4e33a60a7873b1e01b10c5

No code and dts modification.  Just fix the typo in comments.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I70ed20f25244b871a6aa8cd46b27c99838d5fbb6

Pick from facebook/openbmc-linux@720c68c4154b. Only BIC driver related
code is merged in this patch. Use i3c-ast-bridge-ic.c for Aspeed
AST2600/1030/1060 target mode device driver. The legacy driver
i3c-ibi-mqueue.c is removed and no longer used.

Original commit message is as follows
```
kernel-5.15: Support i3c driver (#2446)

Summary:
- Synchronize i3c driver to Aspeed SDK v08.03, linux version v00.05.03.
- Add hot join broadcast attribute to activate BIC I3C controller.
- Add Aspeed BIC driver for BIC write/read function.

X-link: https://github.com/facebookexternal/openbmc.wiwynn/pull/2446

Reviewed By: williamspatrick

Differential Revision: D42433852

Pulled By: garnermic

```

Change-Id: I5d696bbfdcb38c1c7daaa58345dee998cc344fa2

Replace "ibi-mqueue" by "mqueue" to avoid confusion. The mqueue stands
for message queue, for either read (ibi) or write (private write)
accesses.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I5952c9c33cf62949a53f9f8a60a5a5c553883176

Use the SETMRL ccc to inform the device that the packet length of the
driver can afford. The packet length contains the IBI payload and the IBI
pending read.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I27d4312d1ad873fa4f28fccff3a51f52827431f8

When an IBI status is received with the PEC error flag set, further
matching with the mdb table to ensure the pec error actually occurred.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I77373dbc33b26f3556a5b7498cbb9adf3fb4d2a5

Add JESD300 SPD5118 devices (in I2C mode) to I3C bus 2&3, which are
operated in I2C mode

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I143c92f2f39397e0feea822138be43e2a3275dd1

1. Bind eeprom driver for imx3102 i2c mode
2. Correct the address width. It uses 8-bit address for i2c accesses and
16-bit address for i3c accesses.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9492a84164a196d246737f72674ac7cf47c1b580

Remove regmap related code since they had never been used.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Idf5477e065ead9d4485d8f2cf07a4f6eea0ef64b

1. Correct the speed enum to match the hardware design. Noted that it
doesn't match the latest HCI definition.

2. Correct the speed of the CCCs. Only SETHID and DEVCTRL CCCs should
use I2C FM speed. SETAASA uses I3C SDR speed.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I1815d77a7faf3b1a6c7c57182056b592de1f7b3e

Add dual/quad SPI mode for w25q64jvm.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I5d68cd0fca525625d655f8c8b4c2a0ebcc5b282c

The "enable bit" of the I3C slave mode needs to wait for the IBI free time
before it can be activated by the SCL signal. So, this patch add the API
to isolate the SCL/SDA to achieve it.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I52cf2eec4e4f4fd3f3589f362be0a55769872989

Use aspeed_i3c_isolate_scl_sda(...) to enable/disable the software force
mode.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Iff375a016c2116482deb93a5bb715cdaca991589

The enable bit of the i3c slave mode require the scl and stop sequences
to active, but we can't control the scl in slave mode. So, this patch add
support for toggling SCL and generating stop sequences for internal bus
operations which won't affect external signal to active the bit.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Ia6c00c7445be3e0708f00c1093ac4710dff6857f

Implement spidelay by ndelay in order to generate
stable SPI clock waveform sequence. Certainly, it
can be replaced by other more precise delay.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I42133afdd3c7a18a9455e42fad6fca6da1366bcd

Enable OP-TEE driver support.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I2712807564b183e8f5934f7dbd5102001239d65c

The tasklet is scheduled always with RX data interrupt.
The RX data availability check within is redundance and thus removed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I4b295ac0ddcd696937626be5f09d8404d3ecab0f

Avoid priv_xfer occupying the bus and causing the slave ibi transfer to
get stuck.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I6cc927dfbb9cebf34fb0720372c885f5663b8c9c

To minimize code duplication and improve the maintainability of the
driver, this patch consolidate the common flow for enabling/disabling the
i3c slave controller into the 'aspeed_i3c_master_enable' and
'aspeed_i3c_master_disable' APIs.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: I05e63e6ddf7740a25b8afaee6cd45a493d929223

Change the MPS and MRRS optimization strategy to SAFE mode which will use
largest MPS that boot-time devices support.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Ibb7dd8081f5194ebc3953994ebecfa4a08e39885

Change-Id: Ie3f7966ce15ebafad6c36e93e7897503085dfeed
Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com>

1. remove static memory
2. remove pattern search
3. remove tasklet
4. enlarge DMA buffer size to 256KB

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Iadde135e55202b233e7bbd5d19124c0c0cad1cca

Missing ast2600-dcscm-amd in Makefile

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Change-Id: Ibd33418446830c5ef39c58fdff31b1faf79ce440

Porting ast2600-dcscm a2 demo board for Intel Avenue City platform.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Change-Id: I359c439ae17c2d1deb5fa1b355061d1d1aa1906b

According to the specification DSP0238 Chapter 6.7: From the assertion
“Fundamental Reset” until the PCIe fabric has been configured and
enumerated, no “MCTP over PCI Express” messages can be sent.
For error prevention this patch remove the aspeed_mctp_rx_trigger when
MCTP driver probe, ensuring that it can only be called when PCIe obtains
the BDF

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Change-Id: Ia1afdc360b152ddca17098afc38bcc74db0e2f53

Revise driver probe to make sure FIFO is allocated
before interrupt enabling.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I0a22d529c260b7990dcdc386ba0bee69435a24b3

The current implementation limits to maximum 4 KCS channels support.
However, AST2600 has 8 KCS channels and AST2700 has 16. This patch
revise the driver to support more KCS channels.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Ia73dafc1b51803f346117ab9d93e6b0d1eedf43e

Add channel number for KCS nodes.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I64f09d0eab3c7a335ba33f49d6c005c4a3ee87ff

i3c1 is connected to AST1060 i3c2 on dcscm board, and it is
used for testing MCTP over i3c(PFR 4.0 feature).

Per Intel PFR specification, PFR is the i3c master and BMC is
i3c slave.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I1f483af3c38af65d3f95d63c7925e11712602c2c

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Change-Id: Ie12f7659ba735094976f8bca5d9dfc37ed86e2dd

set bus width 1 for spi1 and adds partition for testing
configure i3c1 as slave for ast2600-dcscm-amd

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Change-Id: Iaabcf969d1c643e6e570710f560d241eea85b605

1.Check the smbus block length with I2C_SMBUS_BLOCK_MAX.
If the length is larger than I2C_SMBUS_BLOCK_MAX, then return
-EPROTO.

Signed-off-by: Tommy Huang <tommy_huang@aspeedtech.com>
Change-Id: Iea09059c1ccca8f3aa635aed08a8ddef0ebf1a5d

1. Update the report functionality with I2C_FUNC_SMBUS_BLOCK_PROC_CALL.

Signed-off-by: Tommy Huang <tommy_huang@aspeedtech.com>
Change-Id: I1294ed0b9c889bccb1960982dfdad0af94996c1b