zynq-7000
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This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
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Sep 3, 2019 - VHDL
Deep Learning Processing Unit (DPU IP) integration with Application Processing Unit (APU) using (Zynq-7000 PS) in Xilinx Vivado Design Suite
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Sep 1, 2021 - VHDL
A ZYNQ 7020 project that plays breakout via HDMI.
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Apr 13, 2022 - VHDL
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
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Apr 5, 2022 - VHDL
Projects System On Chip (Zynq700)
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Oct 1, 2020 - VHDL
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